Abstract
The invention relates to a metal layer stack for use in electronic components, in particular as a spacer in power electronic components, comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two. Additionally, the invention relates to a process for preparing the metal layer stack and a semiconductor module comprising such a metal layer stack.
Claims
1. A metal layer stack for use in electronic components comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two.
2. The metal layer stack according to claim 1, wherein where the contact material layer comprises a sinter material.
3. The metal layer stack according to claim 1, wherein the mean thickness of the contact material layer is in the range from 10 μm to 100 μm.
4. The metal layer stack according to claim 1, wherein the bulk metal layer comprises a metal selected from the group consisting of copper, molybdenum, tungsten, silver, aluminium and combinations thereof.
5. The metal layer stack according to claim 1, where the mean thickness of the bulk metal layers is in the range from 50 μm to 600 μm.
6. The metal layer stack according to claim 1, wherein the sinter material is a sinter precursor or a sintered joint.
7. The metal layer stack according to claim 1, wherein the sinter material comprises a metal selected from the group consisting of silver, copper, aluminium, tin, indium, bismuth, nickel and zinc.
8. A semiconductor module wherein a first surface of a semiconductor chip is in contact with a first contact material layer of the metal layer stack according to claim 1.
9. The semiconductor module according to claim 8, wherein a substrate is attached to the last contact material layer of the metal layer stack.
10. The semiconductor module according to claim 8, wherein at least one gate runner is arranged between the semiconductor chip and the metal layer stack.
11. The semiconductor module according to claim 8, wherein the metal layer stack functions as a spacer.
12. The semiconductor module according to claim 8, wherein a second surface of the semiconductor chip opposite to the first surface contacts a second substrate.
13. The semiconductor module according to claim 8, wherein one or more substrates of the semiconductor module are selected from the group consisting of metal ceramic substrates, organic substrates, insulated metal substrates, lead frames and ceramic substrates.
14. A precursor for a spacer comprising a metal layer stack according to claim 1, wherein at least the first or the last contact material layer of the metal layer stack comprises a sinter precursor.
15. A process for producing a metal layer stack, preferably according to claim 1, the process comprising the steps of: a) providing a carrier, b) providing a first layer assembly comprising a contact material precursor layer arranged on a bulk metal layer, c) arranging the layer assembly on the carrier such that the contact material precursor layer is in contact with the carrier, d) providing a second layer assembly comprising a contact material precursor arranged on a bulk metal layer, e) arranging the second layer assembly on the bulk metal layer of the first layer assembly such that the contact material precursor of the second layer assembly is in contact with the bulk metal layer of the first layer assembly, and f) optionally repeating steps d) and e).
16. The process according to claim 15, comprising a step g) of converting the contact material precursor layers into layers of joint material.
Description
BRIEF DESCRIPTION
[0084] In the drawings:
[0085] FIG. 1 illustrates a semiconductor module;
[0086] FIG. 2 illustrates a metal stack of the module shown in FIG. 1;
[0087] FIG. 3 illustrates a gate runner of the module shown in FIG. 1;
[0088] FIG. 4 illustrates an alternative embodiment of a semiconductor module;
[0089] FIG. 5 illustrates a semiconductor module having bulk metal layers; and,
[0090] FIG. 6 illustrates a schematic for producing a metal layer stack and a semiconductor module.
DETAILED DESCRIPTION
[0091] FIG. 1 shows a semiconductor module comprising a metal layer stack (1), a semiconductor chip (20) and substrates (10 and 10′). The semiconductor chip (20) is arranged on a substrate (10). On the opposite surface of the semiconductor chip (20) a metal layer stack (1) is arranged. The metal layer stack (1) contains bulk metal layers (30) and contact material layers (40) wherein the bulk material layers (30) and the contact material layers (40) are stacked in an alternating manner. The last contact material layer (40b) of the metal layer stack (1) is in contact with a substrate (10′). The first contact material layer (40a) is in contact with the semiconductor chip (20).
[0092] FIG. 2 shows a semiconductor module wherein the metal layer stack (1) is located between a substrate (10′) and a semiconductor chip (20) wherein the heights (h) and (h′) differ from each other. The metal layer stack (1) is able to compensate for this height mismatch. The compensation of the height difference is mainly compensated by the contact material layer (40) which exhibit a varying amount of compression. The contact material layers (40) are more compressed on the left side of the semiconductor module compared to the right side. Thus, the overall height (h) is smaller than the overall height h′.
[0093] FIG. 3 displays a semiconductor module wherein a gate runner (21) is located between the metal layer stack (1) and the surface of the semiconductor chip (20). As can be seen the metal layer stack (1) is particularly deformed in the region (22). This enables the metal layer stack (1) to compensate for surface roughness on the semiconductor chip (20). The deformation mainly takes place in the contact material layers (40). Optionally the density of the contact material layers (40) in the region (22) is higher than outside that region. The bulk metal layers (30) mainly bend to adjust to the gate runner (20) but they do not vary significantly in thickness. The fact that the metal layer stack is able to compensate the gate runner (21) in this example the substrates (10) and (10′) can be oriented parallel to each other. Additionally, the fact that the metal layer stack compensates for the height variation due to the gate runner (21) pressure peaks on the semiconductor chip (20) can be prevented.
[0094] FIG. 4 shows another embodiment of the semiconductor module wherein the metal layer stack (1′) comprises additional layers (41). The additional layers (41) are arranged next to the terminal contact material layers of the metal layer stack (1′). The additional layers (41) may for example contain a prefixing agent. In case the additional layers (41) contain a prefixing agent, they can be used to prefix the metal layer stack to the surfaces of the substrate (10′) and the semiconductor chip (20) respectively. Optionally the additional layers (41) can also be located between two bulk metal layers (30) as depicted in FIG. 4. Alternatively, the additional layers (41) are only present in the terminal layers. Furthermore, the semiconductor module shown in FIG. 4 comprises an additional metal layer stack (1) which is arranged on the opposite surface of the semiconductor chip (20). Preferably the contact between metal layer stack 1 and the semiconductor chip (20) is maximized to improve the dissipation of heat generated by the semiconductor chip (20).
[0095] FIG. 5 shows an example of a semiconductor module wherein the bulk metal layers (30) of the metal layer stack (1) are bent towards each other. More specifically the lower two bulk metal layers (30) in FIG. 5 are in contact with each other while the contact material layers (40) are smaller than the bulk metal layers (30).
[0096] FIG. 6 shows a schematic process for producing a metal layer stack and a semiconductor module. In step 6 a) a semiconductor chip (20) on a substrate (10) is provided. In step 6 b) a first layer assembly (50) containing a contact metal layer (40) which is arranged on a bulk metal layer (30). The contact metal layer (40) faces the semiconductor chip. In step 6 c) a further layer assembly (50′) is provided. The further layer assembly (50′) is the last layer assembly which is added to the metal layer stack. Optionally the contact material layers (40) may be arranged on both sides in this further layer assembly (not shown). The further layer assembly (50′) is arranged on the bulk metal layer of the first layer assembly (50). After step 6 d) a metal layer stack (1) is obtained. At the same time a semiconductor module comprising a metal layer stack (1) is obtained. Optionally in step 6 e) another substrate 10′ is arranged on the last layer of the metal layer stack. The substrate in step 6 e) comprises a contact material layer (40b) which may be seen as the last layer of the metal layer stack after conversion of the contact material precursor materials into joint materials. In cases where the last layer assembly of the process comprises contact material layers on both sides of the bulk metal layer, i.e., the terminal layers of the metal layer stack comprise a contact material layer, the further substrate (10′) preferably does not have a contact material layer. Optionally, after step 6 e) the contact metal layers (40) of the metal layer stack may be converted from contact material precursor layers into joint materials. For example, if the contact material layer comprises a sinter precursor it can be converted into a sintered joint by pressure and/or heat (not shown). Step 6 f) shows another embodiment of the semiconductor module according to the invention which may be obtained by the process of the invention.
LIST OF REFERENCE NUMERALS
[0097] (1, 1′) metal layer stack
[0098] (10, 10′) Substrate
[0099] (20) Semiconductor chip
[0100] (21) gate runner
[0101] (22) region (above the gate runner)
[0102] (30) bulk metal layer
[0103] (40) contact material
[0104] (40a) first contact material layer
[0105] (40b) last contact material layer
[0106] (41) additional layer
[0107] (50) first layer assembly
[0108] (50′) further layer assembly
[0109] (h, h′) height of the metal layer stack
