TERAHERTZ DETECTOR USING FIELD-EFFECT TRANSISTOR

Abstract

The purpose of the present invention is to provide a terahertz detector using a field-effect transistor capable of implementing high sensitivity by exhibiting an asymmetric characteristic only with a form of a source/drain and a gate. To this end, the present invention relates to the terahertz detector using a field-effect transistor comprising: a source formed by being doped on a portion of a silicon base; a channel formed so as to encompass the source on a plane; a drain formed outside the channel; a dielectric layer formed on an upper end of the source, the channel and the drain; and a gate located at an upper end of the dielectric layer, wherein when terahertz electromagnetic waves are applied through the gate, the intensity of the electromagnetic waves is detected using a current/voltage outputted from the source and the drain.

Claims

1. A terahertz detector using a field-effect transistor, wherein the field-effect transistor includes: a source formed on a portion of a silicon base through doping; a channel formed to encompass the source on a plane; a drain formed outside the channel; a dielectric layer formed on the source, the channel and the drain; and a gate provided on the dielectric layer, and wherein when a terahertz electromagnetic wave is applied through the gate, an intensity of the electromagnetic wave is detected using a current/voltage outputted from the source and the drain.

2. The terahertz detector of claim 1, wherein the channel is formed to have a predetermined width.

3. The terahertz detector of claim 2, wherein the gate is formed in the same size and shape as the channel.

4. The terahertz detector of claim 2, wherein the gate is formed in the same shape as the channel and a portion of the gate overlaps the source.

5. The terahertz detector of claim 2, wherein the gate is formed in the same shape as the channel and a portion of the gate overlaps the drain.

6. The terahertz detector of claim 2, wherein the gate is formed in the same shape as the channel and a portion of the gate overlaps the source and the drain.

7. The terahertz detector of claim 2, wherein a plane of the source has a circular shape or a polygonal shape.

8. The terahertz detector of claim 3, wherein a plane of the source has a circular shape or a polygonal shape.

9. The terahertz detector of claim 4, wherein a plane of the source has a circular shape or a polygonal shape.

10. The terahertz detector of claim 5, wherein a plane of the source has a circular shape or a polygonal shape.

11. The terahertz detector of claim 6, wherein a plane of the source has a circular shape or a polygonal shape.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0019] FIG. 1 is a cross-sectional view of a terahertz detector according to the present invention,

[0020] FIG. 2 is a top view of FIG. 1,

[0021] FIG. 3 illustrates examples of FIG. 2, and

[0022] FIG. 4 illustrates an example of size definition of FIG. 2.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Referring to FIGS. 1 and 2, a terahertz detector 100 may be implemented through a unit field-effect transistor (FET) formed on a silicon base 1.

[0024] As illustrated in FIG. 1, the FET 10 may include a source 11, a drain 12, a channel 13, a dielectric layer 14, and a gate 15.

[0025] An impurity may be doped into each of the source 11 and the drain 12. The dielectric layer 14 and the gate 13 may be formed of materials generally applicable to an FET. A terahertz electromagnetic wave may be applied to the gate 13. In this instance, a property of the terahertz electromagnetic wave applied by a voltage generated between the source 11 and the drain 12 may be detected.

[0026] As illustrated in FIG. 2, the source 11 may be formed on a center. The channel 13 may be formed to encompass the source 11.

[0027] Thus, the source 11 may be isolatedly provided, and an electrode may be connected via an upper face of the source 11. A cross-section of the source 11 may extend to a lower face of the base 1 such that the electrode is connected via a lower end as necessary.

[0028] As illustrated in FIG. 3, the source 11 may be formed in a circular shape, an oval shape, a triangular shape, a quadrangular shape, and the like, and also be formed in a polygonal shape including a pentagon.

[0029] An inside of the source 11 and an inside of the drain 12 may be formed in different shapes. For example, the inside of the source 11 may be formed in the triangular shape and the inside of the drain 12 may be formed in the quadrangular shape. In this instance, a thickness of the channel 13 may vary.

[0030] Also, depending on examples, the inside of the source 11 and the inside of the drain 12 may have the same shape and origins at different positions. In this instance, the thickness of the channel 12 may also vary.

[0031] When the channel 13 is provided with a predetermined width to encompass the source 11, the channel 13 may be formed to have the same shape as the source 11. Also, in terms of fabrication, it is advantageous to provide the channel 13 with the predetermined width.

[0032] Since the drain 12 is configured based on an area excluding the source 11 and the channel 13, a geometrical asymmetry may be achieved when the source 11 is isolatedly provided as described above.

[0033] The gate 15 may be disposed on the dielectric layer 14 and have the same shape as the channel 13. The gate 15 may have a portion overlapping the source 11 and the drain 12. The overlapping portion may additionally increase the asymmetry.

[0034] When the source 11 is formed in the circular shape, the gate 15 may be formed in a ring shape. As illustrated in FIG. 4, when a diameter of the source 11 is d1, an outer diameter of the channel 13 is d2, an overlap area between the gate 15 and the source 11 is e1, and an overlap area between the gate 15 and the drain 12 is e2, the asymmetry of the FET 10 may be represented by an equation as below.

[0035] In this example, when a length of the source 11 corresponding to one end of the channel 13 is Ws and a length of the drain 12 corresponding to another end of the channel 13 is Wd, a width asymmetry may be defined as a length ratio:

[0036] Width asymmetry=Wd/Ws =πd2/πd1 =d2/d1

[0037] Also, the gate 15 may have an area asymmetry based on the overlapping. The asymmetry of the gate 15 may be defined as a ratio of the overlap area between the gate 15 and the drain 12 to the overlap area between the gate 15 and the source 11.

[0038] The area asymmetry may be calculated as follows.

Area asymmetry=overlap area between the drain 12 and the gate 15/overlap area between the source 11 and the gate 15

Overlap area between the source 11 and the gate 15=π(d1/2).sup.2−π(d1/2.sup.2−eπe1).sup.2

Overlap area between the drain 12 and the gate 15=π(d2/2+e2).sup.2−π(d2/2).sup.2

Thus, area asymmetry=(d2e2+e2.sup.2)/(d1 e1−e1.sup.2)

Here, if e1=e2=e, that is, when the overlap areas are the same, the area asymmetry may be defined as “area asymmetry=(d2+e)/(d1−e)”.

[0039] As the foregoing, since the asymmetry is achieved based on an FET plane shape, the terahertz detector 100 may maintain a sufficient sensitivity without setting for the asymmetry.

[0040] In this example, when a difference between d1 and d2 increases, the width asymmetry may increase. Also, when an overlap value e increases, the area asymmetry may increase. Thus, it is possible to manufacture the terahertz detector 100 having various characteristics by adjusting values of d1, d2, e1, and e2.

[0041] As described above, the terahertz detector 100 may be configured based on silicon process technology. An integration of the terahertz detector 100 with peripheral elements such as an antenna configured to receive a terahertz-wave signal to allow the terahertz-wave signal to flow between an electrode of the gate 15 and an electrode of the source 11, and an amplifier configured to detect output voltage/current between the electrode of the source 11 and a metal electrode of the drain 12 may be implemented on a single silicon substrate based on low-cost silicon process technology. Also, high-sensitivity silicon-based large-area multi-pixel array type detector integration may be realized at low costs based on the low-cost silicon process technology.

[0042] Although a few embodiments of the present invention have been shown and described, the present invention is not limited to the described embodiments. Instead, it would be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.