Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 μm.

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer including a channel region; a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a third nitride semiconductor layer selectively formed on the second nitride semiconductor layer, the third nitride semiconductor layer having a p-type conductivity; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, the fourth nitride semiconductor layer having p-type conductivity and a higher carrier concentration than the third nitride semiconductor layer; a gate electrode formed on the fourth nitride semiconductor layer, the gate electrode being made of a refractory material; and a source electrode and a drain electrode formed on regions of the second nitride semiconductor layer laterally outward of the gate electrode, wherein a width of the gate electrode in a gate length direction is smaller than a width of the third nitride semiconductor layer in the gate length direction, and a difference between the width of the gate electrode in the gate length direction and the width of the third nitride semiconductor layer in the gate length direction is less than or equal to 0.2 μm, wherein the gate electrode has a lower portion being in contact with the fourth nitride semiconductor layer, and including a first metal layer, the first metal layer being made of an alloy containing palladium, the first metal layer has a thickness of 20 nm or less, and the gate electrode has an upper portion includes a second metal layer made of gold or an alloy containing gold.

2. The semiconductor device of claim 1, wherein the second nitride semiconductor layer includes a recessed portion formed in a formation region of the third nitride semiconductor layer, and at least a lower portion of the third nitride semiconductor layer is in the recessed portion of the second nitride semiconductor layer.

3. The semiconductor device of claim 1, wherein the fourth nitride semiconductor layer is in ohmic contact with the gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present disclosure.

(2) FIG. 2 is a graph illustrating annealing temperature dependency of the contact resistivity of p-type GaN and an ITO electrode and the contact resistivity of p-type GaN and an ITO/Au electrode of the semiconductor device according to the first embodiment of the present disclosure.

(3) FIG. 3A is a graph illustrating drain currents and drain voltages before and after application of voltage stress, where the p-type conductive layer is not annealed after etching according to a comparative example. FIG. 3B is a graph illustrating drain currents and drain voltages before and after application of voltage stress, where the p-type conductive layer of the semiconductor device is annealed after etching according to the first embodiment of the present disclosure.

(4) FIGS. 4A-4E are cross-sectional views sequentially illustrating steps in a method for fabricating the semiconductor device according to the first embodiment of the present disclosure.

(5) FIG. 5 is a cross-sectional view illustrating a semiconductor device according to a variation of the first embodiment of the present disclosure.

(6) FIG. 6 is a graph illustrating dependency of the contact resistances of p-type GaN and Pd/Au electrodes of the semiconductor devices on the thickness of Pd films and the annealing temperature according to the variation of the first embodiment of the present disclosure.

(7) FIG. 7 is a SEM micrograph illustrating a cross section of the semiconductor device according to the variation of the first embodiment of the present disclosure.

(8) FIG. 8 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present disclosure.

(9) FIGS. 9A-9G are cross-sectional views sequentially illustrating steps in a method for fabricating the semiconductor device according to the second embodiment of the present disclosure.

(10) FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present disclosure.

(11) FIGS. 11A-11F are cross-sectional views sequentially illustrating steps in a method for fabricating the semiconductor device according to the third embodiment of the present disclosure.

(12) FIG. 12 is a cross-sectional view illustrating a semiconductor device (JFET) according to a first conventional example.

(13) FIGS. 13A-13E are cross-sectional views sequentially illustrating steps in a method for fabricating the semiconductor device according to the first conventional example.

(14) FIG. 14 is a cross-sectional view illustrating a semiconductor device (JFET) according to a second conventional example fabricated by a self-alignment process.

DESCRIPTION

First Embodiment

(15) For example, a field-effect transistor (junction field-effect transistor: JFET) which is a semiconductor device according to a first embodiment of the present disclosure will be described with reference to FIG. 1.

(16) As illustrated in FIG. 1, the field-effect transistor according to the first embodiment includes a 100 nm-thick buffer layer 102 made of AlN, a 2 μm-thick channel layer 103 made of undoped GaN, a 20 nm-thick barrier layer 104 made of undoped AlGaN, a 100 nm-thick p-type GaN layer 105, and a 5 nm-thick p-type GaN layer 106 having a high concentration which are sequentially formed on a substrate 101 made of, for example, silicon (Si).

(17) The p-type GaN layer 105 and the p-type GaN layer 106 having a high concentration are selectively etched to leave portions of the p-type GaN layer 105 and the p-type GaN layer 106 in a gate formation region and expose regions of the barrier layer 104 laterally outward of the left portions of the p-type GaN layer 105 and the p-type GaN layer 106. A gate electrode 111 made of indium tin oxide (ITO) and a gold (Au) electrode 112 are sequentially formed on the p-type GaN layer 106.

(18) A source electrode 108 and a drain electrode 109 which are made of a multilayer film of, for example, titanium (Ti)/aluminum (Al) are formed on the regions of the barrier layer 104 laterally outward of the gate electrode 111 and the p-type GaN layer 105 in a gate length direction. Here, for example, Al.sub.0.15Ga.sub.0.85N can be used for the barrier layer 104 made of undoped AlGaN. Note that as described above, the term “undoped semiconductor” means a semiconductor into which impurities determining the conductivity type are not implanted on purpose. The same applies to the following embodiments.

(19) In order to reduce the expansion of a depletion layer to the p-type GaN layer 105, the carrier concentration of the p-type GaN layer 105 is preferably higher than or equal to 1×10.sup.18 cm.sup.−3. Moreover, the carrier concentration of the p-type GaN layer 106 having a high concentration is preferably higher than or equal to 2×10.sup.18 cm.sup.−3 when an ohmic contact to the gate electrode 111 is obtained.

(20) The field-effect transistor according to the first embodiment includes the p-type GaN layers 105 and 106 between the gate electrode 111 and the barrier layer 104. This can increase the threshold voltage of a gate voltage within a positive value. Specifically, the density of carriers in the p-type GaN layer 105 and the Al composition and the dimension in a thickness direction of the barrier layer 104 are adjusted, and two dimensional electron gas concentration in a portion of the channel layer 103 under the gate electrode 111 is regulated, thereby obtaining a normally-off type transistor.

(21) A first feature of the field-effect transistor according to the first embodiment is that the difference between the width of the gate electrode 111 and the width of the p-type GaN layer 105 is small compared to that in the first conventional example illustrated in FIG. 12, so that the gate electrode 111 and the source electrode 108 or the drain electrode 109 can be formed close to each other. With this configuration, the channel length can be reduced, thereby reducing the channel resistance (source resistance), so that it is possible to increase transconductance. Additionally, the device size is reduced, so that it is possible to increase the number of devices obtained per area.

(22) A second feature of the field-effect transistor according to the first embodiment is that the constituent material of the gate electrode 111 has a high resistance to heat. Nickel (Ni), which has been conventionally used for gate electrodes, is a refractory material having a melting point higher than or equal to 1000° C. However, since Ni has poor adherence, a part of a gate electrode made of Ni peeled off when annealing was performed at a temperature higher than or equal to 700° C. When a multilayer film (Ni/Au electrode) of nickel (Ni) and gold (Au) is used, the adherence is improved, but the homology of a surface of the electrode is significantly degraded when the annealing temperature is higher than or equal to 600° C. When the annealing temperature was higher than or equal to 700° C., a part of an electrode made of the multilayer film of Ni and Au peeled off. Thus, a configuration using Ni as the gate electrode 111 has an insufficient resistance to heat at a temperature equal to or higher than 600° C.

(23) FIG. 2 illustrates annealing temperature dependency of the contact resistivity of the gate electrode structure according to the first embodiment. Specifically, FIG. 2 shows annealing temperature dependency of the contact resistivity of a configuration in which an electrode including only a 100 nm-thick ITO is used as the gate electrode (black triangle shape) and the contact resistivity of a configuration in which a stacked structure including a 100 nm-thick ITO and Au is used as the gate electrode (black diamond shape).

(24) As can be seen from FIG. 2, even when annealing at a temperature higher than or equal to 600° C. was performed, an ohmic contact was obtained in both the configurations, and a sufficient resistance to heat was proved. Thus, even after portions of the p-type GaN layers 105 and 106 are removed by dry etching using the gate electrode 111 as a mask, the gate electrode 111 is not degraded by heat, and thus dry etching damage caused by high temperature annealing can be repaired. Note that it is not necessary that the p-type GaN layer 106 is in ohmic contact with the gate electrode 111. However, when the p-type GaN layer 106 is in ohmic contact with the gate electrode 111, a gate voltage controlling operation of the transistor can be reduced. Therefore, the p-type GaN layer 106 is preferably in ohmic contact with the gate electrode 111.

(25) As described above, according to the field-effect transistor of the first embodiment, the device size can be reduced, and the current collapse can be reduced.

(26) FIG. 3 illustrates the relationship between a drain voltage and a drain current before and after stress is applied by a pulse voltage in the field-effect transistor according to the first embodiment.

(27) FIG. 3A illustrates transistor characteristics obtained when annealing is not performed after removal of the p-type GaN layer according to a comparative example. FIG. 3B illustrates transistor characteristics obtained when annealing is performed in a nitrogen (N.sub.2) atmosphere at 800° C. for 20 minutes after removal of the p-type GaN layer according to the present disclosure. In the comparative example of FIG. 3A, it can be seen that a drain current after application of voltage stress (black square) is significantly lower than that before application of voltage stress (black diamond shape), and so-called current collapse occurs. In contrast, in the present disclosure of FIG. 3B in which high temperature annealing is performed, reduction of the drain current after application of voltage stress (black square) is small, and the current collapse is reduced.

(28) —Fabrication Method—

(29) A method for fabricating a field-effect transistor having the above-described configuration will be described hereinafter with reference to FIGS. 4A-4E.

(30) First, as illustrated in FIG. 4A, for example, by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD), a 100 nm-thick buffer layer 102 made of AlN, a 2 μm-thick channel layer 103 made of undoped GaN, a 20 nm-thick barrier layer 104 made of undoped AlGaN, a 100 nm-thick p-type GaN layer 105, and a 5 nm-thick p-type GaN layer 106 having a high concentration are sequentially formed on a substrate 101 made of Si by epitaxial growth. Note that a material for the substrate 101 may be, but not limited to, silicon (Si). For example, a substrate made of a material, such as sapphire (monocrystalline Al.sub.2O.sub.3), silicon carbide (SiC), or gallium nitride (GaN), which allows epitaxial growth of a nitride semiconductor may be used.

(31) Next, a 2-layer-structure resist film (not shown) is formed on the p-type GaN layer 106 by lithography. The 2-layer-structure resist film has an opening pattern exposing a gate electrode formation region. Subsequently, for example, a 100 nm-thick ITO film and a 100 nm-thick Au film are stacked over the entire surface of the resist film by sputtering, vacuum evaporation, or the like. Then, the resist film and the metal films formed on the resist film are removed by lift-off processing. In this way, as illustrated in FIG. 4B, a gate electrode 111 is made of the ITO film, and an Au electrode 112 is made of the Au film on the gate electrode 111.

(32) Next, as illustrated in FIG. 4C, dry etching using a fluorine-based or chlorine-based gas is performed on the p-type GaN layers 105 and 106 by using the Au electrode 112 and the gate electrode 111 as a mask. In this way, the p-type GaN layers 105 and 106, except their portions under the gate electrode 111, are removed.

(33) Next, as illustrated in FIG. 4D, high temperature annealing is performed on the substrate 101 provided with the Au electrode 112, the gate electrode 111, and the patterned p-type GaN layers 105 and 106, for example, in a nitrogen (N.sub.2) atmosphere at a temperature of 800° C. for 20 minutes. Here, in order to repair damage to the barrier layer 104 made of AlGaN caused by the etching, the annealing temperature is preferably higher than or equal to 650° C. Moreover, to reduce desorption of nitrogen from AlGaN, annealing is preferably performed in a nitrogen atmosphere. Note that at a high temperature higher than or equal to 1100° C., desorption of nitrogen from GaN or AlGaN increases, thereby degrading device characteristics. Therefore, annealing is preferably performed at a temperature lower than or equal to 1100° C. When the Au electrode 112 is formed on the gate electrode 111, annealing is preferably performed at a temperature lower than or equal to 1050° C. because the melting point of Au is 1064° C. When ITO is used for the gate electrode 111, annealing is preferably performed at a temperature lower than or equal to 950° C. because the melting point of the ITO is 980° C.

(34) Next, a 2-layer structure resist film (not shown) having an opening pattern is formed on the barrier layer 104 by lithography, the opening pattern covering at least the Au electrode 112 and exposing formation regions in which a source electrode and a drain electrode will be formed. Subsequently, a multilayer film made of, for example, Ti/Al is formed over the entire surface of the resist film by sputtering, vacuum evaporation, or the like. After that, the resist film and the multilayer film formed on the resist film are removed by lift-off processing. In this way, as illustrated in FIG. 4E, a source electrode 108 and a drain electrode 109 each made of the Ti/Al film are formed. Subsequently, the metals forming the gate electrode 111, the source electrode 108, and the drain electrode 109, and the nitride semiconductor layers are subjected to an alloying process in an infrared alloying furnace or a heat alloying furnace. A field-effect transistor according to the first embodiment can thus be fabricated.

(35) A first feature of the method for fabricating the field-effect transistor according to the first embodiment is that the p-type GaN layers 105 and 106, except their portions in the gate formation region, are removed by using the gate electrode 111 and the Au electrode 112 together as a mask. In this way, a difference between the width of the p-type GaN layers 105 and 106 in the gate length direction and the width of the gate electrode 111 in the gate length direction can be reduced compared to the case where the gate electrode 111 is formed by lift-off processing on the gate formation region of the p-type GaN layers 105 and 106 which have been formed. As a result, the distance between the gate electrode 111 and the source electrode 108 or the drain electrode 109 can be reduced. Note that, the difference between the width of the gate electrode 111 in the gate length and the width of the p-type GaN layers 105 and 106 in the gate length is smaller than or equal to 0.2 μm. Although the difference between the width of the gate electrode 111 in the gate length direction and the width of the p-type GaN layers 105 and 106 in the gate length direction depends on constituent materials of the gate electrode 111, there are only a few cases where the difference is larger than 0.2 μm when the p-type GaN layers 105 and 106 are etched in a self-alignment manner using the gate electrode 111 as a mask.

(36) A second feature of the method for fabricating the field-effect transistor according to the first embodiment is that annealing is performed at a high temperature after the p-type GaN layers 105 and 106, except their portions in the gate formation region, are removed. This can repair damage such as a crystal defect formed by dry etching on or in the vicinity of a surface of the barrier layer 104 made of AlGaN.

(37) Thus, when the method for fabricating the semiconductor device according to the present embodiment is used, the device size can be reduced, and the current collapse can be reduced.

(38) Although indium tin oxide (ITO) is used for the gate electrode 111 in the first embodiment, a material for the gate electrode 111 is not limited to ITO. Instead of ITO, for example, at least one material selected from the group consisting of tungsten silicide (W.sub.xSi.sub.1-x), rhenium silicide (Re.sub.xSi.sub.1-x), tantalum silicide (Ta.sub.xSi.sub.1-x), osmium silicide (Os.sub.xSi.sub.1-x), and molybdenum silicide (Mo.sub.xSi.sub.1-x), where 0<x<1, may be used. Since these materials are materials having a high adhesion similar to ITO, it is possible to further reduce peeling off of the gate electrode 111 from the p-type GaN layer 106.

Variation of First Embodiment

(39) A field-effect transistor of a variation of the first embodiment according to the present disclosure will be described hereinafter with reference to FIG. 5. In FIG. 5, the same reference numerals as those shown in FIG. 1 are used to represent equivalent elements and the explanation thereof will be omitted.

(40) As illustrated in FIG. 5, the field-effect transistor according to the present variation uses palladium (Pd) as a constituent material of a gate electrode 107 formed on p-type GaN layers 105 and 106.

(41) FIG. 6 illustrates dependency of the contact resistivities of p-type GaN and Pd/Au electrodes on the thickness of Pd films of the Pd/Au electrodes and the annealing temperature. Note that when the thickness of the Pd film is 100 nm, a part of the electrode peeled off due to annealing at a temperature of 800° C., and thus it was not possible to measure the current-voltage characteristic. Therefore, the case where the thickness of the Pd film is 100 nm is not plotted on the graph. It can be seen from FIG. 6 that when Pd is used as a gate electrode 107, the thickness of the Pd film is preferably smaller than or equal to 20 nm.

(42) FIG. 7 shows a micrograph taken along a cross section of the field-effect transistor according to the present variation by a scanning electron microscope (SEM). It can be seen FIG. 7 that the difference between the width of an upper surface of the p-type GaN layer in the gate length direction and the width of the gate electrode in the gate length direction is less than or equal to 0.2 μm. Here, the thickness of the Pd/Au electrode is less than or equal to 0.22 μm.

(43) When a stacked structure including the gate electrode 107 and a Au electrode 112 formed on the gate electrode 107 is considered to be a gate electrode, for example, side etching of Pd further progresses compared to that of Au depending on etching conditions of dry etching in the field-effect transistor according to the present variation, so that there is a case where the width of an upper surface of the p-type GaN layer 106 is not equal to the width of a lower surface of the gate electrode 107. In this case, the etching condition is changed, for example, such that a bias output of an inductively coupled plasma (ICP) device is increased, so that it is possible to reduce the difference between the width of the p-type GaN layer 106 and the width of the gate electrode 107 at an interface between the p-type GaN layer 106 and the p-type GaN layer 106.

(44) Moreover, before performing dry etching, annealing at a temperature of, for example, 400° C. is performed on the Pd/Au electrode to form an alloy containing Pd on the p-type GaN layers 105 and 106. Then, the progress of the side etching may be stopped.

(45) With these procedures, the width difference between the p-type GaN layers 105 and 106 and the gate electrode 107 can be reduced to 0.2 μm or less.

(46) Note that the alloy containing Pd is, as described above, an alloy containing Pd as a constituent element of the electrode, and includes a mixture in which part of Pd of an electrode material is not alloyed.

Second Embodiment

(47) For example, a field-effect transistor which is a semiconductor device according to a second embodiment of the present disclosure will be described hereinafter with reference to FIG. 8. In FIG. 8, the same reference numerals as those shown in FIG. 1 are used to represent equivalent elements, and the explanation thereof will be omitted.

(48) The field-effect transistor according to the second embodiment includes a barrier layer 104 made of undoped AlGaN to have a thickness of 50 nm and having a recessed portion 104a. On an upper surface of the bather layer 104, a p-type GaN layer 105, a source electrode 108, and a drain electrode 109 are formed. In the recessed portion 104a, a lower portion of the p-type GaN layer 105 is buried.

(49) Here, the thickness of the p-type GaN layer 105 whose lower portion is buried in the recessed portion 104a of the barrier layer 104, that is, the height from the lower surface to the upper surface of the p-type GaN layer 105, is 100 nm. A 5 nm-thick p-type GaN layer 106 having a high concentration is formed on the p-type GaN layer 105, and a gate electrode 111 made of ITO and a Au electrode 112 are sequentially formed on the p-type GaN layer 106.

(50) Similar to the first embodiment, the p-type GaN layers 105 and 106 of the field-effect transistor according to the second embodiment are provided between the barrier layer 104 and the gate electrode. With this configuration, the threshold voltage of a gate voltage can be increased within a positive value.

(51) Moreover, in the second embodiment, in addition to the carrier density in the p-type GaN layer 105 and the Al composition and the dimension in the thickness direction of the barrier layer, the depth of the recessed portion 104a is adjusted, and the two dimensional electron gas concentration in a portion of a channel layer 103 under the gate electrode 111 is regulated, thereby obtaining a normally-off type transistor.

(52) A first feature of the field-effect transistor according to the second embodiment is that the difference between the width of the gate electrode 111 and the width of the p-type GaN layer 105 is small compared to that in the case of the first conventional example illustrated in FIG. 12, so that the gate electrode 111 and the source electrode 108 or the drain electrode 109 can be formed close to each other. With this configuration, the channel length can be reduced, thereby reducing the channel resistance (source resistance), so that it is possible to increase transconductance. Additionally, the device size is reduced, so that it is possible to increase the number of devices obtained per area.

(53) A second feature of the field-effect transistor according to the second embodiment is that the constituent material of the gate electrode 111 has a high resistance to heat. As described later, even after the p-type GaN layers 105 and 106 are patterned by dry etching using the gate electrode 111 as a mask, the gate electrode 111 is not deteriorated by annealing, so that damage to the bather layer 104 caused by dry etching can be repaired by high temperature annealing.

(54) Similar to the first embodiment, it is not necessary that the p-type GaN layer 106 is in ohmic contact with the gate electrode 111. However, when the p-type GaN layer 106 is in ohmic contact with the gate electrode 111, a gate voltage controlling operation of the transistor can be reduced. Therefore, the p-type GaN layer 106 is preferably in ohmic contact with the gate electrode 111.

(55) A third feature of the field-effect transistor according to the second embodiment is that the recessed portion 104a in which the lower portion of the p-type GaN layer 105 is buried is provided in a region of the barrier layer 104 under the gate electrode 111, so that it is possible to reduce concentration of the electric field on an end of the gate electrode 111 facing the drain electrode 109 or an end of the p-type GaN layer 105 facing the drain electrode 109. With this configuration, current collapse due to the concentration of the electric field on an end of the recessed portion 104a in the barrier layer 104 facing the drain electrode 109 can be reduced, or the breakdown of the device can be prevented.

(56) —Fabrication Method—

(57) A method for fabricating the field-effect transistor having the above-described configuration will be described hereinafter with reference to FIGS. 9A-9G.

(58) First, as illustrated in FIG. 9A, for example, by MBE or MOCVD, a 100 nm-thick buffer layer 102 made of AlN, a 2 μm-thick channel layer 103 made of undoped GaN, and a 50 nm-thick bather layer 104 made of undoped Al.sub.0.15Ga.sub.0.85N are sequentially formed on a substrate 101 made of Si by epitaxial growth.

(59) Next, a resist film (not shown) is formed on the bather layer 104 by lithography. The resist film has an opening pattern exposing a formation region of a recessed portion 104a. Using the formed resist film as a mask, dry etching is performed on the barrier layer 104 by using a fluorine-based or a chlorine-based gas, thereby obtaining the state illustrated in FIG. 9B.

(60) Next, as illustrated in FIG. 9C, MBE or MOCVD is performed again such that a 100 nm-thick p-type GaN layer 105 and a 5 nm-thick p-type GaN layer 106 filling at least the recessed portion 104a are sequentially formed on the barrier layer 104 by epitaxial growth.

(61) Next, a 2-layer-structure resist film (not shown) is formed on the p-type GaN layer 106 by lithography. The 2-layer-structure resist film has an opening pattern exposing a gate electrode formation region. Subsequently, for example, a 100 nm-thick ITO film and a 100 nm-thick Au film are formed over the entire surface of the resist film by sputtering, vacuum evaporation, or the like. Then, the resist film and the metal films formed on the resist film are removed by lift-off processing. In this way, as illustrated in FIG. 9D, a gate electrode 111 is made of the ITO film, and an Au electrode 112 is made of the Au film on the gate electrode 111.

(62) Next, as illustrated in FIG. 9E, dry etching using a fluorine-based or chlorine-based gas is performed on the p-type GaN layers 105 and 106 by using the Au electrode 112 and the gate electrode 111 as a mask. In this way, the p-type GaN layers 105 and 106, except their portions under the gate electrode 111, are removed.

(63) Next, as illustrated in FIG. 4D, high temperature annealing is performed on the substrate 101 provided with the Au electrode 112, the gate electrode 111, and the patterned p-type GaN layers 105 and 106, for example, in a nitrogen (N.sub.2) atmosphere at a temperature of 800° C. for 20 minutes. In order to repair damage to the barrier layer 104 made of AlGaN caused by the etching, the annealing temperature is preferably higher than or equal to 650° C. Moreover, to reduce desorption of nitrogen from AlGaN, annealing is preferably performed in a nitrogen atmosphere. Note that at a high temperature higher than or equal to 1100° C., desorption of nitrogen from GaN or AlGaN increases, thereby degrading device characteristics. Therefore, annealing is preferably performed at a temperature lower than or equal to 1100° C. When the Au electrode 112 is formed on the gate electrode 111, annealing is preferably performed at a temperature lower than or equal to 1050° C. because the melting point of Au is 1064° C.

(64) Next, a 2-layer structure resist film (not shown) having an opening pattern is formed on the barrier layer 104 by lithography, the opening pattern covering at least the Au electrode 112 and exposing formation regions in which a source electrode and a drain electrode will be formed. Subsequently, a multilayer film made of, for example, Ti/Al is formed over the entire surface of the resist film by sputtering, vacuum evaporation, or the like. After that, the resist film and the multilayer film formed on the resist film are removed by lift-off processing. In this way, as illustrated in FIG. 9G, a source electrode 108 and a drain electrode 109 each made of the Ti/Al film are formed. Subsequently, the metals forming the gate electrode 111, the source electrode 108, and the drain electrode 109, and the nitride semiconductor layers are subjected to an alloying process in an infrared alloying furnace or a heat alloying furnace. A field-effect transistor according to the second embodiment can thus be fabricated.

(65) A first feature of the method for fabricating the field-effect transistor according to the second embodiment is that the p-type GaN layers 105 and 106, except their portions in the gate formation region, are removed by using the gate electrode 111 and the Au electrode 112 together as a mask. In this way, a difference between the width of the p-type GaN layers 105 and 106 in the gate length direction and the width of the gate electrode 111 in the gate length direction can be reduced compared to the case where the gate electrode 111 is formed by lift-off processing on the gate formation region of the p-type GaN layers 105 and 106 which have been formed. As a result, the distance between the gate electrode 111 and the source electrode 108 or the drain electrode 109 can be reduced. Note that, the difference between the width of the gate electrode 111 in the gate length and the width of the p-type GaN layers 105 and 106 in the gate length is smaller than or equal to 0.2 μm. Although the difference between the width of the gate electrode 111 in the gate length direction and the width of the p-type GaN layers 105 and 106 in the gate length direction depends on constituent materials of the gate electrode 111, there are only a few cases where the difference is larger than 0.2 μm when the p-type GaN layers 105 and 106 are etched in a self-alignment manner using the gate electrode 111 as a mask.

(66) A second feature of the method for fabricating the field-effect transistor according to the second embodiment is that a high temperature annealing is performed after the p-type GaN layers 105 and 106, except their portions in the gate formation region, are removed. This can repair damage such as a crystal defect formed by dry etching on or in the vicinity of a surface of the barrier layer 104 made of AlGaN.

(67) A third feature of the method for fabricating the field-effect transistor according to the second embodiment is that the recessed portion 104a in which the lower portion of the p-type GaN layer 105 is buried is provided in a region of the barrier layer 104 under the gate electrode 111, so that it is possible to reduce concentration of the electric field on an end of the gate electrode 111 facing the drain electrode 109 or an end of the p-type GaN layer 105 facing the drain electrode 109. With this configuration, the current collapse due to the concentration of the electric field on an end of the recessed portion 104a in the barrier layer 104 facing the drain electrode 109 can be reduced, or the breakdown of the device can be prevented.

(68) Thus, when the method for fabricating the semiconductor device according to the present embodiment is used, the device size can be reduced, and the current collapse can be reduced.

(69) Although ITO is also used for the gate electrode 111 in the second embodiment, a material for the gate electrode 111 is not limited to ITO. Instead of ITO, for example, at least one material selected from the group consisting of tungsten silicide (W.sub.xSi.sub.1-x), rhenium silicide (Re.sub.xSi.sub.1-x), tantalum silicide (Ta.sub.xSi.sub.1-x), osmium silicide (Os.sub.xSi.sub.1-x), and molybdenum silicide (Mo.sub.xSi.sub.1-x, where 0<x<1 may be used. Since these materials are materials having a high adhesion similar to ITO, it is possible to further reduce peeling off of the gate electrode 111 from the p-type GaN layer 106.

Third Embodiment

(70) For example, a field-effect transistor which is a semiconductor device according to a third embodiment of the present disclosure will be described hereinafter with reference to FIG. 10. In FIG. 10, the same reference numerals as those shown in FIG. 1 are used to represent equivalent elements, and the explanation thereof will be omitted.

(71) In the field-effect transistor according to the third embodiment, tungsten (W) which is a refractory material having a particularly high melting point is used as a constituent material of a gate electrode 113 formed on p-type GaN layers 105 and 106.

(72) The field-effect transistor according to the third embodiment includes the p-type GaN layers 105 and 106 between the gate electrode 113 and a barrier layer 104. This can increase the threshold voltage of a gate voltage within a positive value. Specifically, the density of carriers in the p-type GaN layer 105 and the Al composition and the dimension in a thickness direction of the barrier layer 104 are adjusted, and two dimensional electron gas concentration in a portion of a channel layer 103 under the gate electrode 113 is regulated, thereby obtaining a normally-off type transistor.

(73) A first feature of the field-effect transistor according to the third embodiment is that the difference between the width of the gate electrode 113 and the width of the p-type GaN layer 105 is small compared to that in the first conventional example illustrated in FIG. 12, so that the gate electrode 113 and a source electrode 108 or a drain electrode 109 can be formed close to each other. With this configuration, the channel length can be reduced, thereby reducing the channel resistance (source resistance), so that it is possible to increase transconductance. Additionally, the device size is reduced, so that it is possible to increase the number of devices obtained per area.

(74) A second feature of the field-effect transistor according to the third embodiment is that the constituent material of the gate electrode 113 has a high resistance to heat. As described later, even after the p-type GaN layers 105 and 106 are patterned by dry etching using the gate electrode 113 as a mask, the gate electrode 113 is not deteriorated by annealing, so that damage to the bather layer 104 caused by dry etching can be repaired by high temperature annealing.

(75) Similar to the first embodiment, it is not necessary that the p-type GaN layer 106 is in ohmic contact with the gate electrode 113. However, when the p-type GaN layer 106 is in ohmic contact with the gate electrode 113, a gate voltage controlling operation of the transistor can be reduced. Therefore, the p-type GaN layer 106 is preferably in ohmic contact with and the gate electrode 113.

(76) —Fabrication Method—

(77) A method for fabricating a field-effect transistor having the above-described configuration will be described hereinafter with reference to FIGS. 11A-11F.

(78) First, as illustrated in FIG. 11A, for example, by MBE or MOCVD, a 100 nm-thick buffer layer 102 made of AlN, a 2 μm-thick channel layer 103 made of undoped GaN, a 20 nm-thick bather layer 104 made of undoped Al.sub.0.15Ga.sub.0.85N, a 100 nm-thick p-type GaN layer 105, and a 5 nm-thick p-type GaN layer 106 having a high concentration are sequentially formed on a substrate 101 made of Si by epitaxial growth.

(79) Next, as illustrated in FIG. 11B, a 100 nm-thick tungsten (W) film 113A is formed on the p-type GaN layer 106 by sputtering.

(80) Next, a resist film (not shown) masking a gate electrode formation region is formed on the W film 113A by lithography. Subsequently, using the formed resist film as a mask, dry etching is performed on the W film 113A by using a fluorine-based or chlorine-based gas. In this way, as illustrated in FIG. 11C, a gate electrode 113 is formed from the W film 113A. Note that as a gate electrode formation mask, a 100 nm-thick electrode made of an electrode material less susceptible to etching by a fluorine-based or chlorine gas, e.g., gold (Au) may be formed instead of the resist film by lift-off processing. In this case, similar to the field-effect transistor of FIG. 1, a Au electrode is formed on the gate electrode 113.

(81) Next, as illustrated in FIG. 11D, dry etching using a fluorine-based or chlorine-based gas is performed on the p-type GaN layers 105 and 106 by using the gate electrode 113 as a mask. In this way, the p-type GaN layers 105 and 106, except their portions under the gate electrode 113, are removed.

(82) Next, as illustrated in FIG. 11E, high temperature annealing is performed on the substrate 101 provided with the gate electrode 113 and the patterned p-type GaN layers 105 and 106, for example, in a nitrogen atmosphere at a temperature of 800° C. for 20 minutes. Here, in order to repair damage to the barrier layer 104 made of AlGaN caused by the etching, the annealing temperature is preferably higher than or equal to 650° C. Moreover, to reduce desorption of nitrogen from AlGaN, annealing is preferably performed in a nitrogen atmosphere. Note that at a high temperature higher than or equal to 1100° C., desorption of nitrogen from GaN or AlGaN increases, thereby degrading device characteristics. Therefore, annealing is preferably performed at a temperature lower than or equal to 1100° C. When an Au electrode is formed on the gate electrode 113, annealing is preferably performed at a temperature lower than or equal to 1050° C.

(83) Next, a 2-layer structure resist film (not shown) having an opening pattern is formed on the barrier layer 104 by lithography, the opening pattern covering at least the gate electrode 113 and exposing formation regions in which a source electrode and a drain electrode will be formed. Subsequently, a multilayer film made of, for example, Ti/Al is formed over the entire surface of the resist film by sputtering, vacuum evaporation, or the like. After that, the resist film and the multilayer film formed on the resist film are removed by lift-off processing. In this way, as illustrated in FIG. 11F, a source electrode 108 and a drain electrode 109 each made of the Ti/Al film are formed. Subsequently, the metals forming the gate electrode 113, the source electrode 108, and the drain electrode 109, and the nitride semiconductor layers are subjected to an alloying process in an infrared alloying furnace or a heat alloying furnace. A field-effect transistor according to the third embodiment can thus be fabricated.

(84) A first feature of the method for fabricating the field-effect transistor according to the third embodiment is that the p-type GaN layers 105 and 106, except their portions in the gate formation region, are removed by using the gate electrode 113 as a mask. In this way, a difference between the width of the p-type GaN layers 105 and 106 in the gate length direction and the width of the gate electrode 113 in the gate length direction can be reduced compared to the case where the gate electrode 111 is formed by lift-off processing on the gate formation region of the p-type GaN layers 105 and 106 which have been formed. As a result, the distance between the gate electrode 113 and the source electrode 108 or the drain electrode 109 can be reduced. Note that, the difference between the width of the gate electrode 113 in the gate length and the width of the p-type GaN layers 105 and 106 in the gate length is smaller than or equal to 0.2 μm. Although the difference between the width of the gate electrode 113 in the gate length direction and the width of the p-type GaN layers 105 and 106 in the gate length direction depends on constituent materials of the gate electrode 113, there are only a few cases where the difference is larger than 0.2 μm when the p-type GaN layers 105 and 106 are etched in a self-alignment manner using the gate electrode 113 as a mask.

(85) A second feature of the method for fabricating the field-effect transistor according to the third embodiment is that a high temperature annealing is performed after portions of the p-type GaN layers 105 and 106 are removed except portions of the p-type GaN layers 105 and 106 in the gate formation region. This can repair damage such as a crystal defect formed by dry etching on or in the vicinity of a surface of the bather layer 104 made of AlGaN.

(86) Thus, when the method for fabricating the semiconductor device according to the present embodiment is used, the device size can be reduced, and the current collapse can be reduced.

(87) Although tungsten (W) is used for the gate electrode 113 in the third embodiment, a material for the gate electrode 113 is not limited to W. Instead of W, for example, at least one material selected from the group consisting of rhenium (Re), tantalum (Ta), osmium (Os), and molybdenum (Mo) may be used.

(88) Moreover, the variation of the first embodiment and the third embodiment may have a configuration in which a lower portion of the p-type GaN layer 105 is buried in a recessed portion 104a of the barrier layer 104.