Insulated Gate Structure, Wide Bandgap Material Power Device With the Same and Manufacturing Method Thereof

Abstract

An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 10.sup.18 atoms/cm.sup.−3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Claims

1-14. (canceled)

15. An insulated gate structure comprising: a wide bandgap material layer comprising a channel region of a first conductivity type; a gate insulating layer arranged directly on the channel region, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10.sup.18 atoms/cm.sup.−3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stochiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and an electrically conductive gate electrode layer over the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

16. The insulated gate structure according to claim 15, wherein the first nitride layer has a thickness that is less than 20 nm.

17. The insulated gate structure according to claim 15, wherein the first nitride layer has a thickness that is less than 5 nm.

18. The insulated gate structure according to claim 15, wherein the gate insulating layer further comprises an intermediate insulating layer on the first nitride layer, wherein the intermediate insulating layer is made of a material different from that of the first nitride layer.

19. The insulated gate structure according to claim 18, further comprising a second nitride layer is arranged directly on the intermediate insulating layer so that the intermediate insulating layer is sandwiched between the first nitride layer and the second nitride layer.

20. The insulated gate structure according to claim 18, wherein the wide bandgap material layer is a silicon carbide layer and the intermediate insulating layer comprises a high-k dielectric layer that has a dielectric constant higher than that of Si.sub.3N.sub.4.

21. The insulated gate structure according to claim 18, wherein the wide bandgap material layer is a silicon carbide layer and the intermediate insulating layer comprises a silicon oxide layer.

22. A wide bandgap material power device comprising: a wide bandgap material layer comprising a channel region of a first conductivity type and a source region and a drain region of a second conductivity different than the first conductivity type, the source region spaced from the drain region by the channel region; a gate insulating layer arranged directly on the channel region, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10.sup.18 atoms/cm.sup.−3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stochiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and an electrically conductive gate electrode layer over the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

23. The device according to claim 22, wherein: the wide bandgap material layer is a silicon carbide layer; the gate insulating layer further comprises an intermediate insulating layer on the first nitride layer and a second nitride layer arranged directly on the intermediate insulating layer; and the intermediate insulating layer comprises a high-k dielectric layer that has a dielectric constant higher than that of Si.sub.3N.sub.4.

24. A method for manufacturing an insulated gate structure, the method comprising: forming a gate insulating layer arranged directly on a channel region of a wide bandgap material layer, the gate insulating layer comprising a first nitride layer that is arranged directly on the channel region, wherein the gate insulating layer has a concentration of carbon atoms that is less than 10.sup.18 atoms/cm.sup.−3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer and wherein the first nitride layer comprises a stochiometric silicon nitride layer, an aluminum nitride layer, a boron nitride layer or a phosphorous nitride layer; and forming an electrically conductive gate electrode layer over the gate insulating layer.

25. The method according to claim 24, wherein forming the gate insulating layer comprises: depositing a preliminary layer directly on the channel region of the wide bandgap material layer, wherein the preliminary layer comprises silicon, aluminum, boron, or phosphorous or any combination thereof; and nitriding the preliminary layer in a nitrogen containing atmosphere to form the first nitride layer.

26. The method according to claim 25, wherein the nitriding is performed at a temperature in a range between 800° C. and 1400° C.

27. The method according to claim 25, wherein the preliminary layer comprises an amorphous silicon layer.

28. The method according to claim 25, wherein depositing the preliminary layer comprises depositing a layer having a thickness of less than 15 nm.

29. The method according to claim 28, wherein depositing the preliminary layer comprises depositing a layer having a thickness of less than 3.75 nm.

30. The method according to claim 25, wherein forming the gate insulating layer further comprises forming a second nitride layer on the preliminary layer before the nitriding.

31. The method according to claim 25, wherein forming the gate insulating layer further comprises forming a silicon oxide layer on the preliminary layer before the step of nitriding.

32. The method according to claim 25, wherein forming the gate insulating layer further comprises forming an intermediate insulating layer on the first nitride layer.

33. The method according to claim .sub.32, wherein forming the gate insulating layer further comprises forming a second nitride layer on the intermediate insulating layer so that the intermediate insulating layer is sandwiched between the first nitride layer and the second nitride layer.

34. The method according to claim 32, wherein the intermediate insulating layer is a high-k dielectric layer having a dielectric constant higher than that of Si.sub.3N.sub.4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Detailed embodiments of the invention will be explained below with reference to the accompanying figures, in which:

[0031] FIG. 1 shows a flow chart of a known method for manufacturing a stack-gate MIS structure;

[0032] FIG. 2 illustrates the structure of the known stack-gate MIS structure;

[0033] FIG. 3 shows SIMS measurement results for the structure shown in FIG. 2;

[0034] FIG. 4A shows a cross-section of an insulated gate structure according to a first embodiment;

[0035] FIG. 4B shows a cross-section of an insulated gate structure according to a second embodiment;

[0036] FIG. 4C shows a cross-section of an insulated gate structure according to a third embodiment;

[0037] FIG. 5A illustrates SIMS measurement results for a sample of the insulated gate structure according to an exemplary embodiment;

[0038] FIG. 5B illustrates SIMS measurement results for a reference sample;

[0039] FIG. 6 shows a cross-section of a silicon carbide power device comprising an insulated gate structure according to an exemplary embodiment;

[0040] FIG. 7 shows a flow chart illustrating a method for manufacturing an insulated gate structure according to the first embodiment;

[0041] FIG. 8 shows a flow chart illustrating a method for manufacturing an insulated gate structure according to the second embodiment;

[0042] FIG. 9 shows a flow chart illustrating a method for manufacturing an insulated gate structure according to the third embodiment;

[0043] FIG. 10 shows a flow chart illustrating a modification of the method illustrated in FIG. 7; and

[0044] FIG. 11 shows a flow chart illustrating a modification of the method illustrated in FIG. 9.

[0045] The reference signs used in the figures and their meanings are summarized in the list of references signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0046] In the following an insulated gate structure 101a according to a first embodiment is described with reference to FIG. 4A. The insulated gate structure 101a comprises a wide bandgap material layer 50 comprising a channel region 53, a gate insulating layer 100a on the wide bandgap material layer 50 and an electrically conductive gate electrode layer 200 on the gate insulating layer 100a. The wide bandgap material may be exemplarily silicon carbide (SiC), Gallium oxide (GaO), Gallium nitride (GaN) or diamond. In the following description of the examples of embodiments, the wide bandgap material is SiC. However, the invention is not limited to this specific wide bandgap material. The silicon carbide layer 50 may have any known polytype such as a cubic polytype 3C—SiC or any hexagonal polytype such 2H—SiC, 4H—SiC, or 6H—SiC. The gate insulating layer 100a comprises at least a first nitride layer 102 and is arranged directly on the channel region 53. The first nitride layer 102 comprises a silicon nitride layer, such as stoichiometric Si.sub.3N.sub.4, or an aluminum nitride layer (AlN) or a boron nitride (BN) layer or a phosphorous nitride (PN) layer. The first nitride layer 102 may also comprise a combination of two or more of silicon, aluminum, phosphorous and boron. The gate electrode layer 200 is separated from the silicon carbide layer 50 by the gate insulating layer 100a and may comprise any electrically conductive material such as doped poly-silicon or a metal material. A concentration of carbon atoms in the gate insulating layer bow is less than 10.sup.18 atoms/cm.sup.−3 at a distance of 3 nm from an interface 501 between the silicon carbide layer 50 and the first nitride layer 102. Compared to the known insulated gate structures with a gate insulating layer on silicon carbide, the gate insulating layer 100a has a relatively low carbon concentration close to the interface 501 between the silicon carbide layer 50 and the gate insulating layer bow, which results in a high carrier mobility in the channel region 53.

[0047] In FIG. 4B there is shown an insulated gate structure 101b according to a second embodiment. In the following mainly differences to the first embodiment are described, whereas it is referred to the description of the first embodiment with regard to all other features. The insulated gate structure 101b differs from the insulated gate structure 101a according to the first embodiment in that that the gate insulating layer 100b has a two-layered structure comprising the first nitride layer 102 directly on the channel region 53 of the silicon carbide layer 50 and an intermediate insulating layer 104 on the first nitride layer 102. The intermediate insulating layer 104 may comprise any insulating material different from that of the first nitride layer 102. Exemplarily, the intermediate insulating layer comprises an oxide such as silicon dioxide (SiO.sub.2) or a high-k dielectric material, such as aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or titanium oxide (TiO.sub.2). Throughout the specification a high-k-dielectric material is defined as any dielectric material that has a dielectric constant higher than that of Si.sub.3N.sub.4, which is about 7.2.

[0048] A thickness d1 of the first nitride layer 102 is exemplarily less than 20 nm or less than 10 nm, or less than 5 nm. Exemplarily, the thickness d1 of the first nitride layer 102 is at least 3 nm.

[0049] As in the first embodiment, a concentration of carbon atoms in the gate insulating layer 100b is less than 10.sup.18 atoms/cm.sup.−3 or less than 5×10.sup.16 atoms/cm.sup.−3 or less than 10.sup.15 atoms/cm.sup.−3 at a distance of 3 nm from an interface 501 between the silicon carbide layer 50 and the first nitride layer 102. Compared to the known insulated gate structures with a gate insulating layer on silicon carbide, the gate insulating layer 100b has a relatively low carbon concentration close to the interface 501 between the silicon carbide layer 50 and the gate insulating layer 100a, which results, as in the first embodiment, in a high carrier mobility in the channel region 53.

[0050] In FIG. 4C there is shown an insulated gate structure 101c according to a third embodiment. In the following mainly differences to the second embodiment are described, whereas it is referred to the description of the second embodiment with regard to all other features. The insulated gate structure 101c differs from the before described insulated gate structure 101b according to the second embodiment in that it comprises in addition to the first nitride layer 102 a second nitride layer 106 on the intermediate insulating layer 104, so that the intermediate insulating layer 104 is sandwiched between the first nitride layer 102 and the second nitride layer 106. The gate electrode layer 200 is separated from the intermediate insulating layer 104 by the second nitride layer 106. A thickness d2 of the second nitride layer 106 is exemplarily at least 3 nm. The second nitride layer 106 can efficiently block any impurities from the gate electrode layer 200. Exemplarily, when the gate electrode layer 200 comprises highly doped poly silicon, the second nitride layer 106 efficiently blocks diffusion of dopant from the highly doped poly-silicon of gate electrode layer 200 into the intermediate insulating layer 104. In such manner, the second nitride layer increases the life time of the device by preventing degradation of the gate insulation layer 100c due to impurities diffused into the intermediate insulating layer 104, while the material of the intermediate insulating layer 104 can be freely chosen to have desired dielectric properties of the gate insulating layer 100c. As in the second embodiment the intermediate insulating layer 104 may comprise silicon dioxide or a high-k dielectric material, for example.

[0051] FIG. 5A shows SIMS measurement results illustrating the concentration of silicon (Si) atoms, oxygen (O) atoms and carbon (C) atoms in a region adjacent to the interface 501 between the channel region 53 and the gate insulating layer 100b for a specific sample according to the second embodiment. In this specific example the first nitride layer 102 is a Si.sub.3N.sub.4 layer having a thickness d1 of 5 nm and the intermediate insulating layer 104 is a SiO.sub.2 layer. The graph in FIG. 5A shows an intensity value (in arbitrary units) indicative of the concentration of oxygen, silicon and carbon in the sample depending on the position (nm). A position of 52 nm in the graph of FIG. 5A corresponds to the interface between the silicon carbide layer 50 and the first nitride layer 102 of the gate insulating layer 100b. That means, positions above 52 nm correspond to positions within the silicon carbide layer 50 and positions below 52 nm correspond to positions within the gate insulating layer 100b. The drop of the carbon concentration signal (C signal) from a relatively high value in the silicon carbide layer 50 to a relatively low value in the intermediate insulating layer 104 takes place within about 3 nm.

[0052] As a comparison, FIG. 5B shows SIMS measurement results for a comparative reference sample without the first nitride layer 102, i.e. a SiO.sub.2 layer is formed directly on a SiC layer in the reference sample. In FIG. 5B a position of 51.5 nm corresponds to the position of an interface between the SiC layer and the SiO.sub.2 layer. Positions below 51.5 nm are positions within the SiO.sub.2 layer and positions above 51.5 nm are positions within the SiC layer. As can be seen clearly in FIG. 5B, in the graph for the reference sample, the carbon concentration drops significantly slower from a relatively high value in the SiC layer to a relatively low value in the SiO.sub.2 layer.

[0053] FIG. 6 shows a silicon carbide power device according to an exemplary embodiment in cross-section. The silicon carbide power device according to the exemplary embodiment is a silicon carbide based vertical power MISFET 1000, comprising a silicon carbide (SiC) layer 50 having a first main side 58 and a second main side 59 opposite to the first main side 58. The silicon carbide layer 50 comprises adjacent to the first main side 58 an n-type source region 54 comprising an n-type first source region 54a and an n-type second source region 54b, a p-type channel region 53 comprising a p-type first channel region 53a and a p-type second channel region 53b and an n-type drain region 51. The p-type first channel region 53a is laterally sandwiched between the n-type first source region 54a and the n-type drain region 51, and the p-type second channel region 53b is laterally sandwiched between the n-type drain region 51 and the n-type second source region 54b.

[0054] At the second main side 59 of the SiC layer 50 there is arranged a highly doped n-type drain layer 52, on which is arranged a drain electrode layer 30 on the second main side 59. On a side of the drain layer 52 opposite to the drain electrode layer 30 is arranged an n-type drift layer 57. The first source region 54a and the second source region 54b are in electrical contact to a source electrode layer 32 arranged on the first main side 58. On the first main side 58 there is further arranged a gate insulating layer 100 directly on the first channel region 53a and on the second channel region 53b.

[0055] A gate electrode layer 200 is formed on the gate insulating layer 100 to be separated from the first channel region 53a and from the second channel region 53b by the gate insulating layer 100. The first channel region 53a, the gate insulating layer 100 and the gate electrode layer 200 form an insulated gate structure in form of a first insulated gate structure, and the second channel region 53b, the gate insulating layer 100 and the gate electrode layer 200 form an insulated gate structure in form of a second insulated gate structure in the vertical power MISFET 1000. The first and the second insulated gate structures are respectively structured in accordance with any one of the first, second or third embodiment. Therefore, for details regarding the structure of the first and second insulated gate structure it is referred to the discussion of the insulated gate structure according to the first to third embodiment as described above.

[0056] In the following a method for manufacturing the insulated gate structure 101a according to the first embodiment is described with reference to FIG. 7. The method comprises a first step S100 of providing a silicon carbide layer 50 comprising a channel region 53 of a first conductivity type. The silicon carbide layer 50 may have any one of the existing polytypes such as the cubic polytype 3C—SiC or any one of the hexagonal polytypes 2H—SiC, 4H—SiC, or 6H—SiC, for example.

[0057] In a second step S200, a preliminary layer is formed directly on the channel region 53. The preliminary layer comprises a silicon layer or an aluminum layer or a boron nitride layer or a phosphorous layer. Exemplarily, the preliminary layer may be an amorphous silicon layer deposited on the silicon carbide layer 50. A thickness of the preliminary layer is exemplarily less than 15 nm or less than 7.5 nm or less than 3.75 nm, and is exemplarily at least 2 nm.

[0058] In a third step S300 a nitridation of the preliminary layer is performed to form a first nitride layer. In case that the preliminary layer is a silicon layer, the first nitride layer is a silicon nitride layer such as stoichiometric Si.sub.3N.sub.4, in case that the preliminary layer is an aluminum layer the first nitride layer is an aluminum nitride (AlN) layer, in case that the preliminary layer is a boron layer, the first nitride layer is a boron nitride (BN) layer, and in case that the preliminary layer is a phosphorous layer, the first nitride layer is a phosphorous nitride (PN) layer. The resulting thickness of the first nitride layer is exemplarily less than 20 nm, less than 10 nm or less than 5 nm. Nitridation in the third step S300 is exemplarily performed in a nitrogen containing atmosphere such as in N.sub.2 at a temperature in a range between 800° C. and 1400° C., or in a range between 900° C. and 1350° C. Alternatively, nitridation may be performed in a plasma assisted process in a nitrogen containing atmosphere at a temperature between 200° C. and 500° C. Such plasma assisted process may be followed by an annealing in nitrogen containing atmosphere at a higher temperature in a range between 800° C. and 1400° C., or in a range between 900° C. and 1350° C.

[0059] The two-step process of forming the first nitride layer 102, which comprises the second step S200 of forming the preliminary layer and of the subsequent third step S300 of nitridation ensures that no reaction with the silicon carbide layer 50 takes place and no or only very little carbon from the silicon carbide layer 50 is incorporated into the gate insulating layer bow. As the inventors found out, such process in which no or only little carbon from the silicon carbide layer 50 is incorporated in the gate insulating layer results in a relatively high carrier mobility in the channel region.

[0060] In a fourth step S400 a second nitride layer 106 is formed on the first nitride layer 102 by a deposition process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). The second nitride layer 106 may comprise the same nitride material as the first nitride layer 102. In case that the second nitride layer 106 is a silicon nitride layer, it may be formed by PECVD from SiH.sub.4 and NH.sub.3, for example.

[0061] In a fifth step S500, the resulting layer stack including the first nitride layer 102 and second nitride layer 106 is annealed in nitrogen (N.sub.2) to densify and heal defects in the first and second nitride layers.

[0062] Finally, in a sixth step S700, a gate electrode layer 15 is formed on the second nitride layer 106 to obtain an insulated gate structure as shown in FIG. 1, for example. In case that the first nitride layer 102 and the second nitride layer 106 comprise the same nitride material then the resulting gate insulating layer bow comprises only one single continuous nitride layer, whereas if the first nitride layer 102 and the second nitride layer 106 comprise different nitride materials, the resulting gate insulating layer bow has a two-layered structure with two distinguishable nitride layers similar to the gate insulating layer mob shown in FIG. 4B.

[0063] The resulting insulated gate structure 101a exhibits a high carrier mobility in the channel region 50 as discussed above.

[0064] FIG. 8 shows a flow chart illustrating a method for manufacturing the insulated gate structure 101b according to the second embodiment. Due to many similarities with the method discussed before, only differences to the method discussed above with reference to FIG. 7 are explained. The method of FIG. 8 differs from the method of FIG. 7 in that no second nitride layer is formed on the first nitride layer 102, but instead an intermediate insulating layer 104 is formed on the first nitride layer 102 in a fourth method step 400′, wherein the intermediate insulating layer 104 may comprise any insulating material different from the first nitride layer 102. Exemplarily, the intermediate insulating layer 104 may comprise a SiO.sub.2 layer or a high-k dielectric layer or a nitride layer of a nitride material different from that of the first nitride layer 102. A process for forming a SiO.sub.2 layer or a high-k dielectric layer or a nitride layer (different from that of the first nitride layer 102) is known to the person skilled in the art.

[0065] FIG. 9 shows a flow chart illustrating a method for manufacturing the insulated gate structure low according to the third embodiment. Due to many similarities with the method discussed before, only differences to the method discussed above with reference to FIG. 8 are explained. The method of FIG. 9 differs from the method of FIG. 8 in that it further comprises a step S600 performed after the step S500 of annealing in N.sub.2 and before the step S700 of forming the gate electrode layer 200 on the gate insulating layer 100c. In step S600 a second nitride layer 106 is formed on the intermediate insulating layer 102. A process for forming the second nitride layer 106 is not limited to any specific process and may be formed by a process known to the skilled person, for example. A thickness d2 of the second nitride layer 106 may exemplarily be at least 3 nm. As discussed above with reference to FIG. 4C, the second nitride layer 106 prevents incorporation of impurities into and damage of the intermediate insulating layer 104 and the first nitride layer 102. Exemplarily, if the gate electrode layer 200 formed in step S700 is formed of highly doped poly-silicon, the second nitride layer 106 may block incorporation of dopant from the gate electrode layer 200 into the intermediate insulating layer 104 and into the first nitride layer 102 of the gate insulating layer 100c.

[0066] FIG. 10 shows a flow chart illustrating a modification of the method illustrated in FIG. 7. Due to many similarities with the method discussed above with reference to FIG. 7, only differences thereto are explained in the following. The method of FIG. 10 differs from the method of FIG. 7 only in that a step S250 of forming the second nitride layer 106 is performed before a step S300′ of nitridation of the preliminary layer. That means that the second nitride layer is formed on the preliminary layer and only after forming the second nitride layer on the preliminary layer, the nitridation of the preliminary layer is performed in step S300′. The inventors found out that nitridation of the preliminary layer is surprisingly possible through the second nitride layer on the preliminary layer. Such method may be most efficient in preventing any incorporation of carbon from the silicon carbide layer 50 into the gate insulating layer bow and a high carrier mobility in the channel region can be achieved. Alternatively a silicon oxide layer may be formed in step S250 on the first insulating layer before the step S300′ of nitridation of the preliminary layer as indicated in FIG. 10 (see step S250).

[0067] FIG. 11 shows a flow chart illustrating a modification of the method illustrated in FIG. 9. Due to many similarities with the method discussed above with reference to FIG. 9, only differences thereto are explained in the following. The method of FIG. 11 differs from the method of FIG. 9 only in that it comprises an additional step 150 of annealing the silicon carbide layer 50 in N.sub.2 before the step S200 of forming the preliminary layer on the silicon carbide layer 50.

[0068] In an exemplary embodiment a method for manufacturing a silicon carbide power device may comprise any one of the above exemplary embodiments of methods for forming an insulated gate structure. In case that the silicon carbide power device is a MISFET as shown in FIG. 6 or a silicon carbide power device comprising a MISFET, the silicon carbide layer 50 provided in step S100 may comprise a first conductivity type source region 54a, 54b and a first conductivity type drain region 51 adjacent to the second conductivity type channel region 53a, 53b, so that the channel region 53a, 53b is sandwiched between the source region 54a, 54b and the drain region 51, wherein the first conductivity type is different from the second conductivity type.

[0069] In the above embodiments the silicon carbide power device was described to be a vertical power MISFET. However, the concept of the invention may also be applied to any other SiC power device comprising an insulated gate structure, such as to a lateral power MISFET, a gate-all around MISFET, a tri-gated MISFET or an insulated gate bipolar thyristor (IGBT).

[0070] It will be apparent for persons skilled in the art that modifications of the above described embodiment are possible without departing from the scope of the invention as defined by the appended claims.

[0071] The additional method step S150 of annealing the silicon carbide layer 50 in N.sub.2 before the step of forming the preliminary layer was discussed only as a modification of the method of FIG. 9. However, the additional step S150 may be performed also for any of the other described methods for manufacturing an insulated gate structure.

[0072] In all above embodiments the conductivity types may be switched, i.e. in any embodiment, all n-type regions may be p-type and all p-type regions may be n-type.

[0073] It should be noted that the term “comprising” does not exclude other elements or steps and that the indefinite article “a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined.

LIST OF REFERENCE SIGNS

[0074] 1 stack-gate MIS structure

[0075] 10 insulating layer

[0076] 12 SiN.sub.x layer

[0077] 13 SiO.sub.xN.sub.y layer

[0078] 14 SiO.sub.2 layer

[0079] 15 gate electrode layer

[0080] 20 substrate

[0081] 25 interface

[0082] 30 drain electrode

[0083] 32 source electrode

[0084] 50 wide bandgap material layer

[0085] 51 drain region

[0086] 52 buffer layer

[0087] 53, 53a, 53b channel region

[0088] 54a, 54b source region

[0089] 57 drift layer

[0090] 58 first main side

[0091] 59 second main side

[0092] 100, 100a, 100b, 100c gate insulating layer

[0093] 101a, 101b, 101c insulated gate structure

[0094] 102 first nitride layer

[0095] 104 intermediate insulating layer

[0096] 106 second nitride layer

[0097] 200 gate electrode layer

[0098] 501 interface

[0099] 1000 vertical power MISFET

[0100] d1 thickness (of first nitride layer 102)

[0101] d2 thickness (of second nitride layer 104)