Abstract
A capacitor having improved linear properties is provided. The capacitor is compatible with manufacturing processes of components which function using BAW. The capacitor comprises a first and a second electrode (E1, E2) in a first electrically conductive layer and a third electrode (E3) in a second electric layer. A dielectric layer (DL) is arranged between the electrically conductive layers. The first electrode (E1) and the second electrode (E2) are the terminal electrodes of the capacitor.
Claims
1. An apparatus comprising: a bulk acoustic wave (BAW) resonator stack comprising a first electrode, a second upper electrode, a lower electrode, and a piezoelectric layer disposed between the first upper electrode and the lower electrode; a mirror structure disposed below the lower electrode of the BAW resonator stack and comprising a dielectric layer, wherein the dielectric layer is not piezoelectric; and a capacitor electrically connected to the BAW resonator stack and comprising: first and second electrically conductive layers, wherein the dielectric layer of the mirror structure is disposed between the first and second electrically conductive layers; a first electrode and a second electrode disposed in the first electrically conductive layer; and a third electrode disposed in the second electrically conductive layer, wherein: a portion of the first electrode and a portion of the second electrode each overlap with at least a portion of the third electrode; the first electrode and the second electrode are terminal electrodes of the capacitor; the first electrode and the lower electrode are the same electrode; and the second electrode of the capacitor is connected to the second upper electrode through the piezoelectric layer.
2. The apparatus of claim 1, wherein the second upper electrode is electrically connected to the second electrode by a via through the piezoelectric layer, such that the second upper electrode and the lower electrode of the BAW resonator stack are the terminal electrodes of the capacitor.
3. The apparatus of claim 1, wherein the first upper electrode is electrically disconnected from the second electrode and wherein the first upper electrode, the first electrode, and the second electrode comprise at least three terminal electrodes for the apparatus.
4. The apparatus of claim 3, wherein the first upper electrode and the first electrode have a same length.
5. The apparatus of claim 2, wherein the second electrode of the capacitor is electrically connected to a high frequency (HF) filter circuit by the via through the piezoelectric layer.
6. The apparatus of claim 2, wherein the second electrode is electrically connected to a bump connection disposed above a metallization for the via through the piezoelectric layer.
7. The apparatus of claim 1, wherein the dielectric layer is locally thinned in an area associated with the first electrode or with the second electrode.
8. A high frequency (HF) filter circuit comprising the apparatus of claim 1.
9. The HF filter circuit of claim 8, further comprising a rejection circuit or an absorption circuit, wherein the rejection circuit or the absorption circuit comprises the apparatus of claim 1.
10. The HF filter circuit of claim 8, further comprising an inductive element electrically connected in parallel with the capacitor of claim 1.
11. A duplexer matching circuit including a pi-element or a T-element, wherein the duplexer matching circuit comprises the apparatus of claim 1.
12. A duplexer circuit comprising the apparatus of claim 1.
Description
(1) The capacitor is described in greater detail below based on exemplary embodiments, which are to be understood as nonrestrictive, and associated schematic figures.
(2) FIG. 1 shows the essential arrangement of a first, second, and third electrode,
(3) FIG. 2 shows the arrangement of the electrodes in a layer stack,
(4) FIG. 3 shows the use of the capacitor in a BAW resonator stack,
(5) FIG. 4 shows one specific embodiment in which the dielectric layer has a different thickness in different partial capacitors,
(6) FIG. 5 shows one specific embodiment in which the terminal electrodes are electrically connected by means of vias,
(7) FIG. 6 shows the equivalent circuit diagram of the capacitor,
(8) FIG. 7 shows one specific embodiment in which the capacitor is electrically connected in parallel with a BAW resonator,
(9) FIG. 8 shows the equivalent circuit diagram of the electrode structure shown in FIG. 7,
(10) FIG. 9 shows one specific embodiment of a parallel connection of the capacitor to a BAW resonator having three terminals,
(11) FIG. 10 shows the equivalent circuit diagram of the electrode structure of FIG. 9,
(12) FIG. 11 shows one specific embodiment in which one of the electrodes is the extension of a lower electrode of a BAW resonator,
(13) FIG. 12 shows the equivalent circuit diagram of the specific embodiment of FIG. 11,
(14) FIG. 13 shows one specific embodiment of the capacitor having six partial capacitors,
(15) FIG. 14 shows the equivalent circuit diagram of a series connection of the capacitor to a resonator,
(16) FIG. 15 shows one specific embodiment of the capacitor in which the second electrode is arranged beneath a bump connection,
(17) FIG. 16 shows the equivalent circuit diagram of a filter circuit in which the capacitor is electrically connected in parallel with a resonator,
(18) FIG. 17 shows the equivalent circuit diagram of a filter circuit in which the capacitor is electrically connected in a rejection circuit,
(19) FIG. 18 shows the equivalent circuit diagram of a filter in which the capacitor is electrically connected in parallel with an inductive element L2 and in parallel with a resonator X,
(20) FIG. 19 shows the equivalent circuit diagram of a duplexer circuit in which the capacitor is electrically connected in a π-element,
(21) FIG. 20 shows the equivalent circuit diagram of a duplexer in which the capacitor is electrically connected in a T-element,
(22) FIG. 21 shows a filter circuit with the capacitor as a series branch element,
(23) FIG. 22 shows a filter circuit in which the capacitor is electrically coupled to a resonator which is arranged at any location,
(24) FIG. 23 shows a duplexer circuit including the capacitor in a matching circuit.
(25) FIG. 1 schematically depicts the arrangement of the three electrodes of the capacitor. A first electrode E1 and a second electrode E2 are structured in a first electrically conductive layer EL1. A third electrode E3 is structured in a second electrically conductive layer EL2. A dielectric layer DL is arranged between the first electrically conductive layer EL1 and the second electrically conductive layer EL2. At least a portion of the first electrode E1 overlaps with a portion of the third electrode E3. At least a portion of the second electrode E2 likewise overlaps with an additional portion of the third electrode E3. The overlap area of the first electrode E1 and the third electrode E3 essentially forms a plate capacitor, symbolized by the capacitive element C1. The overlap area of the second electrode E2 with the corresponding area of the third electrode E3 likewise forms a plate capacitor, symbolized/depicted by the capacitive element C2. The capacitor of FIG. 1 is thus essentially a series connection of two partial capacitors. The electrodes E1, E2 are the terminal electrodes of the capacitor, via which the capacitor may be electrically connected to a circuit environment. Correspondingly, the first electrode E1 constitutes a first terminal T1, while the second electrode E2 constitutes a second terminal T2. The capacitor thus provides a total capacitance which is a function of the partial capacitances C1, C2, which it is possible to access without a via through the dielectric layer DL.
(26) The material or the materials of the dielectric layer DL and the materials of the electrodes may be selected in such a way that the capacitor has sufficiently good electrical properties even at critical frequencies.
(27) FIG. 2 shows one specific embodiment of the capacitor in which the dielectric layer DL and the third electrode E3 are part of a mirror MIR of a BAW resonator of the mirror type. The mirror MIR is arranged on a substrate SU. The depiction of the mirror MIR is symbolic, i.e., the mirror MIR may comprise additional mirror layers having alternately high and low acoustic impedance.
(28) The capacitance of the capacitor is a function of the overlap areas of the electrodes. The overlap area of the electrodes is in particular a function of the electrode area or its shape and diameter w1, w2. By selecting suitable overlap areas, the desired total capacitance of the capacitor may be set, where the following applies: 1/C.sub.tot=1/C1+1/C2. C.sub.tot is the total capacitance of the capacitor, while C1 and C2 are the corresponding capacitances of the partial capacitors.
(29) A dielectric material and an additional electrode material which is arranged on it may be present above the first electrically conductive layer EL1 for upper electrodes of the resonator stack.
(30) Thus, the upper nonconductive mirror layer of a BAW resonator may be used as a dielectric for the capacitor. The bottom electrode may comprise multiple single layers. The electrical contacting of the capacitor is carried out via the two electrodes E1, E2 as electric terminals. The materials below the mirror are not dependent on the capacitor and may therefore be arbitrary. For manufacturing reasons, a piezoelectric layer which is possibly present above the first electrically conductive layer EL1 may cover an entire wafer in which the component of the capacitor is manufactured and may have recesses, for example, through-etchings, at only a few locations.
(31) FIG. 3 shows one specific embodiment of the capacitor by way of example, in which a piezoelectric layer PZ is arranged above the first electrically conductive layer EL1 with the electrodes E1, E2. In order to obtain a BAW resonator, an additional upper electrode TE is necessary above an electrode arranged beneath the piezoelectric layer, here, the first electrode E1 as the lower electrode BE. If an HF signal is present at the electrodes TE, BE, a standing acoustic wave may develop in the layer stack. The presence of a piezoelectric layer PZ is necessary for developing the acoustic wave, i.e., for the functional capability of the BAW resonator. However, such a piezoelectric layer as a dielectric in the capacitor would result in undesirable nonlinear effects. This arrangement of the dielectric layers and electrode layers relative to each other thus provides a component in which a BAW resonator may be combined and electrically connected to a capacitor which functions in a highly linear manner.
(32) FIG. 4 shows one specific embodiment of the capacitor in which the spacing of the overlapping electrode areas, i.e., the thickness of the dielectric of the two partial capacitors T1, T2, is chosen differently. The resulting capacitance of a partial capacitor is:
C=∈.sub.0∈.sub.rA/D.
(33) A is the overlapping area and ∈.sub.r is the dielectric constant of the dielectric layer, for example, the upper light-conducting mirror layer. The total capacitance of the partial capacitor may be easily set by setting the distance D. The thickness may be reduced to a thickness d1>d2, in particular in an area of the capacitor, for example, via thinning. Thus, the area-specific capacitance of partial capacitors may be increased at least locally.
(34) FIG. 5 shows one specific embodiment of a capacitor in a BAW component, the electrodes E1, E2 having been made accessible using vias through a piezoelectric layer PZ for connecting to additional circuit components. The terminals T1, T2 to the capacitor are thus provided via the metallizations ME in the vias VIA.
(35) The vias VIA through the piezoelectric layer PZ may, for example, be created by etching. It is also possible that the electrodes E1, E2 are created directly by the metallization ME arranged in the vias VIA. The metallizations ME then touch the dielectric layer directly.
(36) A bump connection as shown by way of example, for example, in FIG. 13, may be arranged and electrically connected in the recess of the via.
(37) FIG. 6 shows the equivalent circuit diagram of the capacitor, i.e., a series connection of two partial capacitors between the terminals T1 and T2. The figure thus shows the equivalent circuit diagram of the capacitor from FIG. 5.
(38) FIG. 7 shows one specific embodiment of the capacitor in which the first electrode E1 is simultaneously the lower electrode of an additional layer stack comprising a dielectric material D2 and a metallization of the terminal T2. If the additional dielectric material D2 is piezoelectric, the first electrode E1 is simultaneously the lower electrode of the corresponding BAW resonator stack. The electrode arrangement of FIG. 7 shows a parallel connection of the capacitor to a resonator comprising the dielectric layer D2. FIG. 7 thus depicts a space-saving specific embodiment of a parallel connection of a capacitor to a resonator. Such an electrode arrangement in particular makes possible the targeted reduction of the resonator coupling of the BAW resonator BAW.
(39) Such an arrangement makes it possible to save chip area, because the partial capacitor comprising the electrodes E1 and E3 is arranged directly beneath the resonator BAW. The space beneath the resonator BAW is in fact generally not available for additional BAW resonator stacks because these areas are acoustically coupled to each other.
(40) FIG. 8 shows the equivalent circuit diagram of the electrode structure from FIG. 7.
(41) FIG. 9 shows one specific embodiment in which, unlike the specific embodiment of FIG. 7, the second electrode E2 of the capacitor is not electrically connected to the upper electrode of the BAW resonator BAW. The specific embodiment of FIG. 9 thus constitutes a component having three independent terminals T1, T2, T3.
(42) It is possible that the area of the second electrode E2 exceeds the required area of the terminal T2 by a factor x. x may lie between 1 and 100 and may be in particular 1.1, 2, 5, 10, and 50.
(43) FIG. 10 shows the equivalent circuit diagram of the electrode arrangement of FIG. 9.
(44) FIG. 11 shows one specific embodiment in which the first electrode E1 of the capacitor is obtained as an extension of the lower electrode of a BAW resonator. The BAW resonator comprises a part of the electrically conductive layer including the first electrode E1, material of the piezoelectric layer, and material of an electrode layer on the piezoelectric layer.
(45) FIG. 12 shows the equivalent circuit diagram of the electrode arrangement of FIG. 11. A terminal T3 is electrically connected to the resonator, but not directly to the capacitor. A terminal T2 is electrically connected to the capacitor, but not directly to the resonator. A terminal T1 is electrically connected directly both to the resonator and the capacitor.
(46) FIG. 13 shows one specific embodiment of the capacitor by way of example including six partial capacitors. In addition to the first electrode E1 and the second electrode E2, the first electrically conductive layer EL1 comprises additional electrode structures E. The second electrically conductive layer EL2 correspondingly comprises additional structured electrode sections, so that a corresponding series connection is obtained from six partial capacitors. In this way, a series connection made up of 2n partial capacitors may be easily obtained, where n is a natural number >1.
(47) FIG. 14 shows the equivalent circuit diagram of a possible connection of the capacitor, i.e., a series connection, to a resonator.
(48) FIG. 15 shows one specific embodiment of a capacitor, in which the contacting of the second electrode is implemented via a bump connection BU. The bump connection BU constitutes the second terminal of the capacitor. The bump connection BU may sit directly on the second electrode. It is also possible for the bump connection BU to be arranged on a metallization ME in a recess through the piezoelectric layer PZ. An additional layer, for example, a so-called UBM (under-bump metallization) may be arranged between the bump connection BU and the first electrode E1 or the metallization ME for improving contact between the bump BU and the electrode.
(49) The implementation of the bump connection BU may be carried out via a piece of a bonding wire, via solder, or other conventional manufacturing methods. Since a bump connection advantageously includes a bottom structure, it is recommended to situate one of the electrodes E1, E2 under the bump connection and to move the corresponding section of the uppermost conductive mirror layer under the bump connection as a third electrode E3, in order to obtain a maximum overlapping structure and thus maximum capacitance of the capacitor.
(50) The third electrode E3 comprises an area which is arranged under the bump connection.
(51) FIG. 16 shows an equivalent circuit diagram of a filter circuit F in which a capacitor comprising the two partial capacitors C1, C2 electrically connected in series is electrically connected in parallel with a resonator X as a parallel branch element, for example, in a ladder-type filter structure. The capacitor may thus connect a terminal B which is, for example, electrically connected to a signal path, to a terminal A which is, for example, electrically connected to ground.
(52) An inductive element L for connecting to ground may also be electrically connected between the terminal A and a ground terminal. The direct connection to the resonator X is not necessary. The capacitor may also connect the terminal B directly to the terminal A without additional circuit elements. More than one capacitor according to the present invention may be included in a filter circuit F and in a corresponding component; the dots on the left FIG. 16 correspondingly indicate that the depicted circuit elements constitute only a portion of a more extensive circuit.
(53) FIG. 17 shows a capacitor including the partial capacitors C1 and C2 which is electrically connected in a rejection circuit. The capacitor is electrically connected to the inductive elements L1 and L2. In particular, the capacitor is electrically connected in series between the two inductive elements L1, L2. FIG. 17 depicts the capacitor as part of a rejection circuit, for example, at a filter port FP. The resonance frequency f of the rejection circuit is
(54)
C.sub.x is the static capacitance of the resonator X, and C.sub.tot is 1/(1/C.sub.1+1/C.sub.2). The inductive elements L1, L2 are optional and may be omitted as required or implemented as parasitic inductances, for example, of feed lines. The parallel connection to the resonator X is optional. Without the connection to the resonator X, a correspondingly corrected blocking frequency results.
(55) FIG. 18 shows the equivalent circuit diagram of a filter circuit F, the capacitor including the partial capacitors C1, C2 being electrically connected in parallel with an inductive element L2. The inductive element L2 may be part of an impedance matching circuit between the filter circuit F, for example, a transmission or reception filter, and an additional filter, for example, a corresponding reception or transmission filter of a duplexer. When matching impedance using parallel inductive elements and a filter port, small inductance values cause long lines in the Smith chart. Due to the lack of space in the corresponding component, it is usually not possible to introduce an inductive element having a higher inductance in a corresponding housing. There are also application cases in which a serial inductance for compensation is not possible. The capacitor having good linear properties then provides relief if it is electrically connected in parallel with the corresponding inductive element L2. The specific embodiment of FIG. 18 depicts yet another inductive element L1 which, however, is optional and may be omitted, or which may be implemented via a parasitic inductance, for example, a feed line. The connection of the capacitor to the resonator X is also optional and is not mandatory.
(56) FIG. 19 shows the equivalent circuit diagram of a duplexer circuit including two filter circuits F. The capacitor including the partial capacitors C1 and C2 is part of a π-element circuit, for example, for impedance matching in the antenna port of the duplexer. More precisely, the capacitor is electrically connected in a parallel path of the π-element. An additional capacitive element C is electrically connected in the other parallel path of the π-element. The additional capacitive element C may also be a capacitive element according to the present invention or a conventionally manufactured capacitive element.
(57) FIG. 20 shows the equivalent circuit diagram of a duplexer circuit including two filter circuits F, the capacitor including the partial capacitors C1, C2 being electrically connected in the series path of a T-element matching circuit. An inductive element L is electrically connected in the parallel branch of the T-element. The inductive element according to the present invention is electrically connected in series with a capacitive element C which is conventional or which is also according to the present invention.
(58) FIG. 21 depicts a general equivalent circuit diagram in which the capacitor is electrically connected as a series branch element to any arbitrary additional circuit components.
(59) FIG. 22 symbolizes a circuit arrangement in which the capacitor including the partial capacitors C1, C2 is coupled directly or indirectly to a resonator which is arranged at any location. A spatial proximity between the capacitor and the resonator is not mandatory in order to achieve the advantages of the capacitor. The parallel circuit made up of the resonator and the capacitor may be electrically connected to ground via an inductive element L.
(60) FIG. 23 depicts a duplexer circuit DU having an antenna terminal ANT between a transmission terminal Tx and a reception terminal Rx. A matching circuit including two inductive elements IE and the capacitor including the two partial capacitors C1, C2 is electrically connected to the antenna terminal ANT.
(61) The transmission signal branch functions essentially using bulk acoustic waves, while the reception branch functions using acoustic surface waves. FIG. 23 thus constitutes a hybrid duplexer. A ground element of a ladder-type structure having a triple cascade in the signal path and quadruple cascade in the parallel branch path is electrically connected between the antenna terminal ANT and the reception terminal Rx. A DMS (dual mode SAW) structure is electrically connected between the ground element and the terminal Rx. The reception terminal Rx is balanced. The transmission terminal is unbalanced.
(62) A capacitor according to the present invention is not limited to one of the described exemplary embodiments. Combinations of features of the exemplary embodiments and variations which, for example, comprise additional resonators, inductive or capacitive elements, or partial capacitors, also constitute exemplary embodiments according to the present invention.
LIST OF REFERENCE NUMBERS
(63) A, B: Filter terminals ANT: Antenna terminal BAW: BAW resonator stack, BAW resonator BE: Lower electrode of a BAW resonator stack BU: Bump connection C: Capacitive element C1, C2: First, second partial capacitor D1, D2: Thicknesses of the dielectric layer D2: Additional dielectric material DL: Dielectric layer DMS: DMS structure DU: Duplexer E: Additional structured electrodes in the first electrically conductive layer E1, E2: First, second electrode E3: Third electrode EL1: First electrically conductive layer EL2: Second electrically conductive layer F: Filter f: Blocking frequency IE: Inductive element L1, L2: Inductive element ME: Metallization MIR: Mirror PZ: Piezoelectric layer Rx: Reception terminal SU: Substrate T1, T2: First, second terminal of the capacitor TE: Upper electrode of a BAW resonator stack Tx: Transmission terminal UBM: Under-bump metallization VIA: Via W1, W2: Lateral dimensions of the first, second electrode X: Resonator
