Bipolar transistor and method for producing the same

Abstract

A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

Claims

1. A bipolar transistor comprising: a subcollector layer; a collector layer above the subcollector layer, the collector layer including a plurality of parts, the plurality of parts having impurity concentrations different from each other; and a collector electrode on the subcollector layer; wherein the collector layer includes a portion that extends beyond at least one edge of the plurality of parts in a cross-sectional view, the portion is separated from the collector electrode, the plurality of parts has graded impurity concentrations, and the plurality of parts includes a first part, and the impurity concentration in the first part is higher than an impurity concentration in the subcollector layer.

2. The bipolar transistor according to claim 1, wherein the impurity concentration in the first part is a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer.

3. The bipolar transistor according to claim 1, wherein the impurity concentration in the first part is higher than an impurity concentration in at least one of the plurality of parts and is on a side of or in contact with the subcollector layer.

4. The bipolar transistor according to claim 1, wherein the impurity concentrations of the plurality of parts are higher on a side of the subcollector layer and lower on a side opposite to the subcollector layer.

5. The bipolar transistor according to claim 2, wherein the first part comprises the portion.

6. The bipolar transistor according to claim 3, wherein the first part comprises the portion.

7. The bipolar transistor according to claim 1, wherein the subcollector layer contacts the collector electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of the structure of a bipolar transistor according to an embodiment of the present disclosure.

(2) FIG. 2 graphically represents the distribution of impurity concentrations in some layers of a bipolar transistor according to an embodiment of the present disclosure.

(3) FIG. 3 illustrates the components of the collector resistance of a bipolar transistor according to an embodiment of the present disclosure.

(4) FIG. 4 graphically represents the relationship between ρs1c/ρssc and ρstot/ρssc of a bipolar transistor according to an embodiment of the present disclosure.

(5) FIG. 5 is a cross-sectional view of the structure of a bipolar transistor according to an example of the present disclosure.

(6) FIG. 6 is a cross-sectional diagram illustrating a method for the fabrication of a bipolar transistor according to an example of the present disclosure.

(7) FIG. 7 is a cross-sectional diagram illustrating a method for the fabrication of a bipolar transistor according to an example of the present disclosure.

(8) FIG. 8 is a cross-sectional diagram illustrating a method for the fabrication of a bipolar transistor according to an example of the present disclosure.

(9) FIG. 9 is a cross-sectional diagram illustrating a method for the fabrication of a bipolar transistor according to an example of the present disclosure.

(10) FIG. 10 is a cross-sectional view of the structure of a bipolar transistor according to an example of the present disclosure.

(11) FIG. 11 is a cross-sectional view of the structure of a known bipolar transistor.

(12) FIG. 12 is a cross-sectional view of the structure of a known bipolar transistor.

DETAILED DESCRIPTION

(13) The following describes some embodiments of the present disclosure with reference to the drawings. Like elements are given like numerals throughout and described only once in the following.

(14) FIG. 1 is a cross-sectional view of the structure of a bipolar transistor 100 according to an embodiment of the present disclosure. The bipolar transistor 100 includes a subcollector layer 2, a collector layer 3, a base layer 4, and an emitter layer 5, each being a layer of a compound semiconductor. The subcollector layer 2 has two principal surfaces, one of which is referred to as the first surface 201 and the other as the second surface 202. The second surface 202 is on the side opposite the first surface 201. On the first surface 201, of the subcollector layer 2, are collector electrodes 9. The subcollector layer 2 is on a substrate 1, with the second surface 202 in contact with the substrate 1. The base layer 4 also has two principal surfaces, one of which is referred to as the third surface 401 and the other as the fourth surface 402. The fourth surface 402 is on the side opposite the third surface 401. On the third surface 401 are the emitter layer 5 and base electrodes 10. The collector layer 3 also has two principal surfaces, one of which is referred to as the fifth surface 301 and the other as the sixth surface 302. The sixth surface 302 is on the side opposite the fifth surface 301, with the fifth surface 301 in contact with the fourth surface 402 and the sixth surface 302 in contact with the first surface 201. The collector layer 3 includes multiple doped layers 31, 32, 33, and with graded impurity concentrations, higher on the sixth surface 302 side and lower on the fifth surface 301 side. The doped layers 31, 32, 33, and 34 are stacked in this order on the subcollector layer 2 and referred to as the first, second, third, and fourth doped layers, respectively. These doped layers vary in impurity concentration but are of the same material. On the emitter layer 5 is a stack of a capping layer 12, a contact layer 8, and an emitter electrode 11.

(15) The bipolar transistor 100 is, for example, a hetero-bipolar transistor, in which the emitter layer 5 and the base layer 4 form a heterojunction and the emitter layer 5 has a band gap greater than that of the base layer 4. The heterojunction reduces the base resistance, improving the radio-frequency characteristics of the bipolar transistor 100. Furthermore, the compound semiconductors give the bipolar transistor 100 high electron mobility. The region 101 is referred to as an intrinsic HBT.

(16) FIG. 2 graphically represents the distribution of impurity concentrations in some layers of the bipolar transistor 100. In FIG. 2, the horizontal axis is for depth in the direction from the third surface 401, of the base layer 4, to the first surface 201, of the subcollector layer 2, and the vertical axis for the impurity concentration in each layer. The segments 200, 310, 320, 330, 340, and 400 correspond to the distributions of impurity concentrations in the subcollector layer 2, first doped layer 31, second doped layer 32, third doped layer 33, fourth doped layer 34, and base layer 4, respectively. The doped layers 31, 32, 33, and 34 have a first type of conductivity, and the base layer 4 has a second type of conductivity, opposite the first. For example, when the first type of conductivity is n-type, the second is p-type. When the first type of conductivity is p-type, for example, the second is n-type. As illustrated, the first doped layer 31 has the highest impurity concentration among the multiple doped layers 31, 32, 33, and 34. The impurity concentration in the second doped layer 32 is the second highest, and that in the third doped layer 33 is the third highest. In the fourth doped layer 34, the impurity concentration is the lowest. The impurity concentration in the first doped layer 31 and that in the subcollector layer 2 may be the same or different.

(17) Preferably, the impurity concentration in the subcollector layer 2 is about 1×10.sup.18 cm.sup.−3 or more. Doping the subcollector layer 2 to a high concentration will reduce the collector resistance Rc of the bipolar transistor 100, increasing the output power of the bipolar transistor 100.

(18) Desirably, each of the second, third, and fourth doped layers 32, 33, and 34 has an impurity concentration at least about an order of magnitude smaller than that in the first doped layer 31. This improves the base-collector and collector-emitter breakdown voltages, ensuring the bipolar transistor 100 is not broken even when operated to full output power.

(19) For the second and third doped layers 32 and 33, it is preferred that the impurity concentration be about 1×10.sup.16 cm.sup.−3 or more and about 7×10.sup.16 cm.sup.−3 or less. For the fourth doped layer 34, it is preferred that the impurity concentration be about 3×10.sup.15 cm.sup.−3 or less. Under such conditions, increasing the collector voltage Vc makes the base-collector depletion layer rapidly expand within the fourth doped layer 34, owing to the impurity concentration in the fourth doped layer 34 much lower than those in the second and third doped layers 32 and 33. At a certain low voltage Vca within the saturation region of the bipolar transistor 100, the base-collector depletion layer reaches the boundary between the third and fourth doped layers 33 and 34. In the third doped layer 33, however, the expansion of the base-collector depletion layer at collector voltages Vc higher than or equal to Vca is limited because of the impurity concentration higher than that in the fourth doped layer 34. This means that at collector voltages Vc higher than or equal to Vca, the collector-voltage dependence of the base-collector capacitance Cbc is limited, and the linearity of the base-collector capacitance Cbc is improved. In this way, this adjustment of impurity concentrations makes the bipolar transistor 100 suitable for the application of RF (radio-frequency) signals for those telecommunication standards that require high linearity, such as WCDMA® (Wideband Code Division Multiple Access) and LTE (Long Term Evolution).

(20) Preferably, the impurity concentration in the second doped layer 32 is higher than that in the third doped layer 33. This makes the access resistance R2cac in the second doped layer lower than it is when the second and third doped layers 32 and 33 have the same impurity concentration. The decrease in the access resistance R2cac leads to a decrease in the overall collector resistance Rc of the bipolar transistor 100. The on-state resistance of the bipolar transistor 100 is reduced, and, as a result, the output power of the bipolar transistor 100 is increased. Doping the second doped layer 32 to a high concentration, furthermore, will reduce the loss of on-state breakdown voltage where a large amount of current flows through the bipolar transistor 100, ensuring that even if the load changes when the bipolar transistor 100 is operated to full output power, the collector breakdown voltage upon load mismatch, determined by the on-state breakdown voltage, decreases only to a limited extent.

(21) In each of the doped layers 31, 32, 33, and 34, the impurity concentration does not need to be uniform and may have a gradient. The number of doped layers constituting the collector layer 3 does not need to be four and can be two, three, five, or more.

(22) FIG. 3 illustrates the components of the collector resistance Rc of the bipolar transistor 100. The first doped layer 31 has an impurity concentration and thickness similar to those of the subcollector layer 2 and extends beyond the boundary that separates the intrinsic HBT 101 from the outside. The first doped layer 31 therefore behaves as if it is a low-resistance current path, which is not present in an HBT in the known structure. Each of the resistance components the first doped layer 31 has is denoted by R1cin. Since each resistance component R1cin is connected in parallel to an internal subcollector resistance component Rscin, which lies in the subcollector layer 2, the collector resistance Rc is equal to (Rscex+Rscin/R1cin)/2, where Rscin/R1cin=(Rscin×R1cin)/(Rscin+R1cin). The contribution of Rscac is again negligible compared with that of Rscex+Rscin/R1cin, and so is that of R1cac, for the reason described above. R2cac, in FIG. 3, is inside the thickness required to achieve the desired breakdown voltages. It does not need to be discussed and can be ignored.

(23) The term “similar” as used in expressions like “A is similar to B” herein means that values A and B expressed as powers of ten have the same exponent value. For example, when the value B is about 1/10 or more and about 9 times or less the value A, the values A and B can be deemed as similar.

(24) Rscin/R1cin<Rscin, and Rscac and R1cac are negligible. The collector resistance Rc in this embodiment, (Rscex+Rscin/R1cin)/2, is therefore always smaller than that in the known structure, (Rscex+Rscin)/2+Rcac. Since the first doped layer 31 has an impurity concentration and thickness similar to those of the subcollector layer 2, the bipolar transistor 100 has a structure in which the subcollector layer 2 and the first doped layer 31 are connected in parallel. This parallel connection reduces the collector resistance Rc. In an HBT in the known structure, the doped layer corresponding to the first doped layer 31 has a low impurity concentration compared with the subcollector layer, and, therefore, the resistance components in the subcollector layer predominantly determine the collector resistance. Hence it is difficult to reduce the collector resistance of an HBT in the known structure.

(25) The sheet resistance of the subcollector layer 2 is denoted by ρssc, that of the first doped layer 31 by ρs1c, and the total sheet resistance of the subcollector layer 2 and the first doped layer 31, connected in parallel, by ρstot. FIG. 4 graphically represents the relationship between ρs1c/ρssc and ρstot/ρssc of a bipolar transistor 100 according to this embodiment. As the graph indicates, ρstot/ρssc is asymptotic to 1 at sufficiently high ρs1c/ρssc ratios, about 0.9 at a ρs1c/ρssc of about 9, and sharply drops at lower ρs1c/ρssc ratios. This means that bringing down ρs1c/ρssc to about 9 or less is effective in reducing the collector resistance Rc. At sufficiently low ρs1c/ρssc ratios, ρstot/ρssc is asymptotic to 0. Given the modest decrease, from about 0.1 to about 0, in ρstot/ρssc within the range of ρs1c/ρssc less than about 1/10, ρs1c/ρssc values lower than about 0.1 have little effect in reducing the collector resistance Rc. Since such low ρs1c/ρssc ratios are also technically difficult to achieve, it is preferred that ρs1c/ρssc be about 1/10 or more. Overall, it is preferred that ρs1c/ρssc be about 1/10 or more and about 9 or less. That is, it is preferred that the first doped layer 31 have a sheet resistance about 1/10 or more and about 9 times or less that of the subcollector layer 2. This means that if the first doped layer 31 and the subcollector layer 2 have the same impurity concentration, it is preferred that the first doped layer 31 have a thickness about 1/9 or more and about 10 times or less that of the subcollector layer 2.

(26) At ρs1c/ρssc ratios of about 3 or less, ρstot/ρssc changes greatly with a change in ρs1c/ρssc and is about 0.75 or less. This means that bringing down ρs1c/ρssc to about 3 or less reduces the collector resistance Rc significantly. ρs1c/ρssc ratios lower than about ⅓, however, have little effect in reducing the collector resistance Rc. In this range, the decrease in ρstot/ρssc is modest, from about 0.25 to about 0. Overall, it is preferred that ρs1c/ρssc be about ⅓ or more and about 3 or less. That is, it is preferred that the first doped layer 31 have a sheet resistance about ⅓ or more and about 3 times or less that of the subcollector layer 2. This means that if the first doped layer 31 and the subcollector layer 2 have the same impurity concentration, it is preferred that the first doped layer 31 have a thickness about ⅓ or more and about 3 times or less that of the subcollector layer 2.

(27) Furthermore, forming the first doped layer 31 to a thickness similar to the subcollector layer 2 and in contact with the first surface 201, of the subcollector layer 2, as in FIG. 3 places the base electrodes 10 and base layer 4 farther away from the collector electrodes 9, reducing the external capacitances Cbcex1, and also from the subcollector layer 2, reducing the external capacitances Cbcex2. These reductions in the external capacitances Cbcex1 and Cbcex2 lead to a decrease in the overall base-collector capacitance Cbc of the bipolar transistor 100. The bipolar transistor 100 combines a low collector resistance Rc with a low base-collector capacitance Cbc in this way, and offers high output power, high gain, and high efficiency.

Examples

(28) FIG. 5 is a cross-sectional view of the structure of a bipolar transistor 100 according to this example. As illustrated in the drawing, the bipolar transistor 100 has a semi-insulating GaAs substrate 1 and a stack of an n-type GaAs subcollector layer 2, an n-type GaAs collector layer 3, a p-type GaAs base layer 4, and an n-type In.sub.xGa.sub.1-xP emitter layer 5 on the substrate 1. The n-type GaAs subcollector layer 2 has an Si concentration of about 2×10.sup.18 cm.sup.−3 or more and about 6×10.sup.18 cm.sup.−3 or less and a thickness of about 0.3 μm or more and about 1.0 μm or less. The n-type GaAs collector layer 3 has a thickness of about 900 nm or more and about 1500 nm or less. The p-type GaAs base layer 4 has a C concentration of about 2×10.sup.19 cm.sup.−3 or more and about 5×10.sup.19 cm.sup.−3 or less and a thickness of about 50 nm or more and about 150 nm or less. The n-type In.sub.xGa.sub.1-xP emitter layer 5 has a Si concentration of about 2×10.sup.17 cm.sup.−3 or more and about 5×10.sup.17 cm.sup.−3 or less and a thickness of about 30 nm or more and about 50 nm or less. The proportion of In, x, is about 0.5.

(29) On the n-type In.sub.xGa.sub.1-xP emitter layer 5 is a stack of an n-type GaAs layer 6, an n-type In.sub.xGa.sub.1-xAs grading layer 7, and an n-type In.sub.xGa.sub.1-xAs contact layer 8. The n-type GaAs layer 6 has a Si concentration of about 2×10.sup.18 cm.sup.−3 or more and about 4×10.sup.18 cm.sup.−3 or less and a thickness of about 50 nm or more and about 150 nm or less. The n-type In.sub.xGa.sub.1-xAs grading layer 7 has an Si concentration of about 1×10.sup.19 cm.sup.−3 or more and about 3×10.sup.19 cm.sup.−3 or less and a thickness of about 30 nm or more and about 70 nm or less. The proportion of In, x, is about 0 on the side closer to the p-type GaAs base layer 4 and about 0.5 on the side farther from the p-type GaAs base layer 4. The n-type In.sub.xGa.sub.1-xAs contact layer 8 has a Si concentration of about 1×10.sup.19 cm.sup.−3 or more and about 3×10.sup.19 cm.sup.−3 or less and a thickness of about 30 nm or more and about 70 nm or less. The proportion of In, x, is about 0.5.

(30) The impurity concentration and thickness of the n-type In.sub.xGa.sub.1-xP emitter layer 5 are selected so that this layer is depleted of free electrons outside the area beneath the n-type In.sub.xGa.sub.1-xAs contact layer 8, n-type In.sub.xGa.sub.1-xAs grading layer 7, and n-type GaAs layer 6. Actually, therefore, current flows only through the intrinsic emitter region 51, the portion of the n-type In.sub.xGa.sub.1-xP emitter layer 5 beneath the mesa of the n-type In.sub.xGa.sub.1-xAs contact layer 8, n-type In.sub.xGa.sub.1-xAs grading layer 7, and n-type GaAs layer 6. It should be noted that FIGS. 1 and 3 illustrate the emitter layer 5 as if substantially all of it is the intrinsic emitter region. The depleted region of the emitter layer 5 is not illustrated.

(31) The first, second, third, and fourth doped layers 31, 32, 33, and 34, constituting the collector layer 3, are formed integrally into a mesa as a whole. No additional operation is therefore needed to form the first doped layer 31. The first, second, third, and fourth doped layers 31, 32, 33, and 34 are n-type GaAs layers with different impurity concentrations.

(32) Preferably, the first doped layer 31 has an impurity concentration and thickness similar to those of the subcollector layer 2. This reduces the collector resistance Rc in accordance with Rc=(Rscex+Rscin/R1cin)/2. For example, it is preferred that the first doped layer 31 have an impurity concentration of about 1×10.sup.18 cm.sup.−3 or more and about 5×10.sup.18 cm.sup.−3 or less, such as about 3×10.sup.18 cm.sup.−3, and a thickness of about 200 nm or more and about 900 nm or less, such as about 500 nm.

(33) As for the second, third, and fourth doped layers 32, 33, and 34, it is preferred that each have an impurity concentration at least about an order of magnitude smaller than that in the subcollector layer 2. The second doped layer 32 preferably has an impurity concentration of about 3×10.sup.16 cm.sup.−3 or more and about 7×10.sup.16 cm.sup.−3 or less, such as about 5×10.sup.16 cm.sup.−3, and a thickness of about 100 nm or more and about 300 nm or less, such as about 200 nm. The third doped layer 33 preferably has an impurity concentration of about 1×10.sup.16 cm.sup.−3 or more and about 4×10.sup.16 cm.sup.−3 or less, such as about 1.5×10.sup.16 cm.sup.−3, and a thickness of about 100 nm or more and about 300 nm or less, such as about 220 nm. The fourth doped layer 34 preferably has an impurity concentration of about 3×10.sup.15 cm.sup.−3 or less, such as about 3×10.sup.15 cm.sup.−3, and a thickness of about 300 nm or more and about 500 nm or less, such as about 400 nm.

(34) On the surface of the n-type In.sub.xGa.sub.1-xAs contact layer 8 is an emitter electrode 11. The emitter electrode 11 is, for example, a Ti (about 50 nm thick)/Pt (about 50 nm thick)/Au (about 200 nm thick) electrode. On the surface of the p-type GaAs base layer 4 is a pair of base electrodes 11 facing each other with the intrinsic emitter region 51 therebetween. The base electrodes 10 are, for example, Ti (about 50 nm thick)/Pt (about 50 nm thick)/Au (about 200 nm thick) electrodes. On the surface of the subcollector layer 2 is a pair of collector electrodes 9 facing each other with the collector layer 3 therebetween. The collector electrodes 9 are, for example, AuGe (about 60 nm thick)/Ni (about 10 nm thick)/Au (about 200 nm thick)/Mo (about 10 nm thick)/Au (about 1 μm thick) electrodes.

(35) The following describes a method for the fabrication of a bipolar transistor 100 with reference to FIGS. 6 to 9.

(36) First, as illustrated in FIG. 6, an n-type GaAs subcollector layer 2 is formed on the surface of a GaAs substrate 1. Then first, second, third, and fourth doped layers 31, 32, 33, and 34 are sequentially formed on the n-type GaAs subcollector layer 2 by the same process, giving an n-type GaAs collector layer 3. This way of forming the first doped layer 31 and the other doped layers 32, 33, and 34, sequentially and by the same process, allows the manufacturer to use an existing fabrication method as it is, requiring no additional operation to form the first doped layer 31. Then a p-type GaAs base layer is formed on the fourth doped layer 34, an n-type In.sub.xGa.sub.1-xP emitter layer 5 on the p-type GaAs base layer 4, an n-type GaAs layer 6 on the n-type In.sub.xGa.sub.1-xP emitter layer 5, an n-type In.sub.xGa.sub.1-xAs grading layer 7 on the n-type GaAs layer 6, and an n-type In.sub.xGa.sub.1-xAs contact layer 8 on the n-type In.sub.xGa.sub.1-xAs grading layer 7. The individual layers 2 to 8 of the bipolar transistor 100 are formed by an epitaxial process, such as metal-organic chemical vapor deposition. The dopant for n-type semiconductor layers can be, for example, Si, and that for p-type semiconductors can be, for example, C. The n-type In.sub.xGa.sub.1-xAs contact layer 8 may be doped with Se or Te so that it has a high impurity concentration.

(37) Then, as illustrated in FIG. 7, an emitter electrode 11 is formed on the surface of the n-type In.sub.xGa.sub.1-xAs contact layer 8. The n-type In.sub.xGa.sub.1-xAs contact layer 8, n-type In.sub.xGa.sub.1-xAs grading layer 7, and n-type GaAs layer 6 are then etched, with the etch mask being a photoresist mask (not illustrated), to leave the portion above the intrinsic emitter region 51 and eliminate the unnecessary rest. As a result, a mesa of the n-type In.sub.xGa.sub.1-xAs contact layer 8, n-type In.sub.xGa.sub.1-xAs grading layer 7, and n-type GaAs layer 6 is determined.

(38) Then, as illustrated in FIG. 8, the n-type In.sub.xGa.sub.1-xP emitter layer 5, p-type GaAs base layer 4, and collector layer 3 are etched, with the etch mask being a photoresist mask (not illustrated), to form a mesa and eliminate the unnecessary portion. The first, second, third, and fourth doped layers 31, 32, 33, and 34 are sequentially etched by the same process, and the resulting doped layers 31, 32, 33, and 34 have substantially the same two-dimensional shape when viewed in the direction in which the doped layers 31, 32, 33, and 34 are stacked. This way of forming the first doped layer 31, into substantially the same two-dimensional shape as the other doped layers 32, 33, and 34, allows the manufacturer to use an existing fabrication method as it is, requiring no additional operation to form the first doped layer 31. The n-type In.sub.xGa.sub.1-xP emitter layer 5 is then worked to expose the areas of the p-type GaAs base layer 4 in which base electrodes 10 are to be formed. After that, base electrodes 10 are formed in contact with the p-type GaAs base layer 4 and alloyed to create ohmic contacts.

(39) Then, as illustrated in FIG. 9, collector electrodes 9 are formed in contact with the subcollector layer 2 and alloyed to create ohmic contacts. Lastly, the entire surface of the bipolar transistor 100 is covered with a passivation coating 14, such as a SiN film.

(40) The combination of the materials for the emitter layer and base layer 4 does not need to be InGaP (emitter)/GaAs (base). For the emitter layer 5 and base layer 4, other heterojunction-forming combinations of materials can be also used including AlGaAs (emitter)/GaAs (base), InP (emitter)/InGaAs (base), InGaP (emitter)/InGaAs (base), InGaP (emitter)/GaAsSb (base), InGaP (emitter)/AlGaAs (base), InGaP (emitter)/InGaAsN (base), Si (emitter)/SiGe (base), and AlGaN (emitter)/GaN (base).

(41) The first doped layer 31 may have, as illustrated in FIG. 10, a two-dimensional shape that extends beyond the edges of the two-dimensional shape of the other doped layers 32, 33, and 34 when viewed in the direction in which the doped layers 31, 32, 33, and 34 are stacked. This increases the area of contact between the subcollector layer 2 and the first doped layer 31, providing a further reduction in collector resistance Rc.

(42) While preferred embodiments of the disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The scope of the disclosure, therefore, is to be determined solely by the following claims.