Abstract
A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.
Claims
1-7. (canceled)
8. A method for manufacturing a SiC power device comprising steps of: growing an epitaxial layer of a first conductivity type onto a substrate of said first conductivity type, wherein said epitaxial layer has a lower doping concentration than the substrate; forming a plurality of first type and second type gate trenches by performing following steps: a) forming a trench mask onto a top surface of said epitaxial layer for definition of the plurality of first type gate trenches; b) forming said first type gate trenches in said epitaxial layer by etching through open regions in said trench mask; c) forming a dielectric layer on sidewalls and bottoms of said plurality of first type gate trenches; d) removing said dielectric layer on bottoms of said first type gate trenches by an anisotropic oxide etch; e) performing an anisotropic silicon etch to form a plurality of second type gate trenches.
9. The method of claim 8, further carrying out an angle ion implantation of said second conductivity type dopant into said sidewalls and bottoms of said plurality of second type gate trenches to form a second conductivity type doped region surrounding each of said plurality of second type gate trenches.
10. The method of claim 9, further comprising a zero degree ion implantation of said second conductivity type dopant.
11. The method of claim 8, further depositing a Boron Silicate Glass (BSG) layer into said plurality of second type gate trenches after formation of said plurality of second gate type trenches to form a second conductivity type doped region surrounding sidewalls and bottoms of said plurality of second type gate trenches.
12. The method of claim 8, further comprising the steps of: forming a first insulating film along inner surfaces of said plurality of first type and inside said plurality of second type gate trenches, wherein said plurality of second type gate trenches filled up by said first insulation film; etching back said first insulating film from upper portion of said plurality of first type gate trenches to remove said first insulating film from top surface of said epitaxial layer and sidewalls of said plurality of first type gate trenches; forming a second insulating film as a gate oxide layer on sidewalls of said plurality of first type gate trenches; depositing a doped poly-silicon layer into said plurality of first type gate trenches; and etching back said first doped poly-silicon to form a gate electrode.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
[0019] FIG. 1 is a cross-sectional view of a conventional SiC semiconductor device having a trench gate vertical double diffused MOSFET.
[0020] FIG. 2A is a cross-sectional view of a preferred embodiment according to the present invention.
[0021] FIG. 2B is a cross-sectional view of another preferred embodiment according to the present invention.
[0022] FIG. 3 is a cross-sectional view of another preferred embodiment according to the present invention.
[0023] FIG. 4 is a cross-sectional view of another preferred embodiment according to the present invention.
[0024] FIGS. 5A˜5L are a serial of side cross-sectional views for showing the processing steps for fabricating the SiC SJ trench MOSFET of FIG. 4.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0025] In the following Detailed Description, reference is made to the accompanying drawings, which forms a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purpose of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
[0026] Please refer to FIG. 2A for a preferred embodiment of this invention. A SiC power device comprising an SJ trench MOSFET formed on an N+ type SiC substrate 201 with a less doped N type SiC epitaxial layer 202 extending thereon, wherein the N+ substrate 201 is coated with a back metal 220 of Ti/Ni/Ag on rear side as a drain metal. Inside the N epitaxial layer 202, a plurality of trenches having first type gate trenches 203 and second type gate trenches 204 are formed vertically downward from the top surface of the epitaxial layer 202 and not reaching the interface 216 between the N epitaxial layer 202 and the N+ substrate 201, wherein the width of the first type gate trenches 203 is greater than that of the second type gate trenches 204. A gate electrode 205 is disposed in upper portion of the first type gate trenches 203 and surrounded with a thick bottom oxide as the first insulating film 206 on bottom of the gate trenches 203, and surrounded with a second insulating film 209 on sidewalls of the gate trenches 203, wherein the second insulating film 209 has a less thickness than the first insulating film 206. The second type gate trenches 204 are filled up with the first insulating film 206. Between every two adjacent first type gate trenches 203, a p body region 210 with n+ source regions 211 thereon is extending near top surface of the N epitaxial layer 202 and surrounding the gate electrode 205 padded by the second insulating film 209. An interlayer dielectric film 221 is stacked on the epitaxial layer 202, and the source metal 212 is formed onto the contact interlayer 221. The p body regions 210, the n+ source regions 211 are further shorted to a source metal 212 comprising Ti/TiN/Al alloys through a plurality of trenched contacts 223 filled with contact plugs 213 comprising Ti/TiN/Al alloys and surrounded by heavily doped regions 214 around bottoms underneath the n+ source regions 211. According to the invention, p* regions 215, which is adjacent to sidewalls of the second type gate trenches 204, are introduced into the N epitaxial layer 202 to form a SJ region, comprising a plurality of alternating p* regions 215 and N regions 202 above the N+ substrate 201. According to this embodiment, the SJ region is surrounding with at least lower portion of the second type gate trenches 204, and the p* regions 215 is above the bottom surface 216 of the N epitaxial layer 202. The p* regions 215 can be easily formed along sidewalls and bottoms of the second type gate trenches 204 by an angle ion-implantation or combination of a zero-degree ion implantation of boron through sidewalls and bottoms of the second type gate trenches 204, or by a BSG layer deposition procedure.
[0027] Please refer to FIG. 2B for another preferred embodiment of the present invention, the trenched semiconductor power device has a similar structure to FIG. 2A, except that the trenched source contacts 323 in the present structure are filled with contact plugs 313 comprising Ti/TiN/W layers while the source metal 312 is comprising of Ti/TiN/Al Alloys.
[0028] Please refer to FIG. 3 for another preferred embodiment of the present invention, compared with FIG. 2B, the trenched semiconductor power device in FIG. 3 is formed in an epitaxial layer, which further comprises a lower N1 epitaxial layer 402-1 between the N+ substrate 401 and the SJ region with resistivity R1 and an upper N2 epitaxial layer 402-2 with resistivity R2, wherein R1<R2. Moreover, the SJ region comprises a plurality of alternating p* regions 415 and N2 regions 402-2 above the N1 epitaxial layer 402-1, wherein the p* regions 415 touch to bottom surface 416 of the upper N2 epitaxial layer 402-2. The trenched source contacts 423 in the present structure are filled with contact plugs 413 comprising Ti/TiN/W layers while the source metal 412 is Al Alloys.
[0029] Please refer to FIG. 4 for another preferred embodiment of the present invention, the trenched semiconductor power device has a similar structure to FIG. 3, except that the present structure further includes a p type gate oxide electric field reducing regions 517 (Pr, as illustrated) adjoining lower surfaces of the p body regions 510 and space apart from the trenches. The trenched source contacts 523 in the present structure are filled with contact plugs 513 comprising Ti/TiN/W layers while the source metal 512 is Al Alloys.
[0030] FIGS. 5A˜5K are a serial of exemplary steps that are performed to form the invention embodiment of FIG. 4. In FIG. 5A, an epitaxial layer comprising of a lower N1 epitaxial layer 602-1 with resistivity R1 and an upper N2 epitaxial layer 602-2 with resistivity R2 (R1<R2) is grown onto a N+ type SiC substrate 601, wherein the epitaxial layer has a lower doping concentration than the N+ substrate 601. A p body region 610 and an n+ source region 611 are then formed into the N2 epitaxial layer 602-2 in active area. A hard mask 613 (not shown) such as an oxide layer is formed onto a top surface of the N2 epitaxial layer 602-2 for definition of areas for a plurality of first type gate trenches 603. Then, after dry oxide etch and dry silicon etch, a plurality of first type gate trenches 603 are formed penetrating through open regions in the hard mask, the N2 epitaxial layer 602-2, and not reaching the bottom surface 616 of N2 epitaxial layer 602-2. A sacrificial oxide layer (not shown) is first grown and then removed to eliminate the plasma damage after forming the gate trenches 603.
[0031] In FIG. 5B, a dielectric layer 617 is formed by oxide deposition or thermal oxide growing method on sidewalls and bottoms of the first type gate trenches 603.
[0032] In FIG. 5C, dielectric layer on bottoms of the first type gate trenches 603 is removed by dry oxide etching.
[0033] In FIG. 5D, an anisotropic silicon etch is performed to form a plurality of the second type gate trenches 604.
[0034] In FIG. 5E, an angle ion implantation into sidewalls and bottom of the second type gate trenches 604 and a diffusion step are successively carried out to form a p* region 615 surrounding the second type trenches 604. Moreover, combination of zero degree and angle boron ion implantation would be carried out if bottom of trench 604 is too narrow.
[0035] In FIG. 5F, a BSG layer is deposited into both the two type trenches to provide an alternate way to form a p* region 615 surrounding the second type gate trenches 604.
[0036] In FIG. 5G, the dielectric layer 617 is removed.
[0037] In FIG. 5H, a first insulating film 606 comprising a thick oxide layer is formed along inner surfaces of both the two type gate trenches 603 and 604 and top surface of upper epitaxial layer 602-2 by thermal oxide growth or thick oxide deposition, wherein the second type gate trenches 604 are filled up with the first insulating film 606.
[0038] In FIG. 5I, the first insulating film 606 is etched back from top surface of the epitaxial layer 602-2, and the upper portion of the first type gate trenches 603.
[0039] In FIG. 5J, the second insulating film 609 is then thermally grown or deposited along sidewalls of the first type gate trenches 603 and top surfaces of the N2 epitaxial layer 602-2 as a gate oxide, which is thinner than the first insulation layer 606. After that, a first doped poly-silicon layer is deposited onto the first gate insulating film 606 to fill the upper portions of the first type gate trenches 603, and then etched back by CMP (Chemical Mechanical Polishing) or Plasma Etch or Poly recess etch to serve as the single gate electrodes 605.
[0040] In FIG. 5K, a second dielectric layer such as combination of an undoped oxide layer and a BPSG layer is formed over the entire structure using conventional techniques. After applying a contact mask (not shown) onto the top surface of the epitaxial layer 602-2, the oxide layer is etched back to form the dielectric layer 621. After applying a contact mask (not shown) onto the contact interlayer 621, a plurality of trenched contacts 623 are formed by successively dry oxide etch and dry silicon etch penetrating through the contact interlayer 621, and extending into the p body regions 610 for trenched source-body contacts. A Boron ion implantation is performed to form a p type gate oxide electric field reducing region 617 (illustrated as Pr) adjoining lower surfaces of the p body region 610 and space apart from the trenches 603. Next, another BF2 Ion implantation is performed to a p+ body contact doped region 614 within the p body regions 610 and surrounding at least bottom of the trenched source body-contacts penetrating through the n+ source region 611 and extending into the p body region 610, and Then, a barrier metal layer of Ti/TiN is deposited on sidewalls and bottoms of all the trenched contacts 623 followed by a step of RTA process for silicide formation. Then, a tungsten material layer is deposited onto the barrier layer, wherein the tungsten material layer and the barrier layer are then etched back to form contact metal plug 613 comprising Ti/TiN/W for the trenched source-body contacts.
[0041] In FIG. 5L, a metal layer of Al alloys padded by a resistance-reduction layer Ti or Ti/TiN underneath is deposited onto the contact interlayer 621 and followed by a metal etching process by employing a metal mask (not shown) to be patterned as a source metal 612.
[0042] Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
