WAFER HOLDER AND METHOD

Abstract

A wafer holder for holding a semiconductor wafer during electrochemical porosification with an electrolyte comprises a housing for receiving the semiconductor wafer, an aperture in the housing, through which an upper surface of the semiconductor wafer is exposable to the electrolyte, a seal extending around the aperture, for preventing the ingress of electrolyte into the housing; and an electrical contact for making an electrical connection with the semiconductor wafer. A method of electrochemical porosification of a semiconductor wafer comprises the steps of placing a semiconductor wafer in a wafer holder; immersing the housing in an electrolyte, so that the surface of the semiconductor wafer is exposed to electrolyte through the aperture; and applying a potential difference between the semiconductor wafer and the electrolyte.

Claims

1. A wafer holder for holding a semiconductor wafer during electrochemical porosification with an electrolyte, the wafer holder comprising: a housing for receiving the semiconductor wafer; an aperture in the housing, through which an upper surface of the semiconductor wafer is exposable to the electrolyte; a seal extending around the aperture, for preventing the ingress of electrolyte into the housing; and an electrical contact for making an electrical connection with the semiconductor wafer.

2. A wafer holder according to claim 1, in which the electrical contact is configured to contact the upper surface and/or an outer edge of the semiconductor wafer.

3. A wafer holder according to claim 2, in which the electrical contact is configured to make an electrical connection with the upper surface of the semiconductor wafer between the seal and the edge of the surface.

4. A wafer holder according to claim 1, in which the housing is configured so that the edges of the semiconductor wafer are not exposable to the electrolyte.

5. A wafer holder according to claim 1, in which the aperture is configured to be smaller than the surface of the semiconductor wafer to be received in the housing, so that only a portion of the surface of the semiconductor wafer is exposable to the electrolyte.

6. A wafer holder according to claim 1, in which the electrical contact is configured to make an electrical connection with a portion of the semiconductor wafer that is not exposed to the electrolyte.

7. A wafer holder according to claim 1, in which the electrical contact is provided in a sealed portion of the housing, so that the electrical contact is not exposable to electrolyte.

8. A wafer holder according to claim 1, in which the electrical contact is configured to be biased against the semiconductor wafer.

9. A wafer holder according to claim 1, in which the housing comprises a plurality of electrical contacts arranged to contact the semiconductor wafer at a plurality of positions around its perimeter.

10. A wafer holder according to claim 9, in which the housing comprises two, or three, or four, or five, or six or eight or more electrical contacts arranged around the housing for contacting the semiconductor wafer at a plurality of positions around its perimeter.

11. A wafer holder according to claim 9, in which the plurality of electrical contacts are spaced evenly around the housing to contact the semiconductor wafer at a plurality of equidistant positions.

12. A wafer holder according to claim 1, in which the housing is configured to receive a circular semiconductor wafer with a radius R, and in which the aperture is a circular aperture with a radius r, in which r<R.

13. A wafer holder according to claim 1, in which housing is openable for insertion and removal of semiconductor wafers.

14. A wafer holder according to claim 1, in which the housing comprises a backing section for contacting the bottom surface of the semiconductor wafer, and a front section comprising the aperture, for contacting the upper surface of the semiconductor wafer.

15. A wafer holder according to claim 14, in which the backing section and the front section of the housing are connectable to one another by a plurality of releasable fasteners.

16. A wafer holder according to claim 14, in which the backing section of the housing comprises a compressible member for supporting the bottom surface of the semiconductor wafer.

17. A wafer holder according to claim 1, comprising an electrical lead for connecting the electrical contacts to a power source.

18. A wafer holder according to claim 1, in which the housing is formed from acid-resistant plastic.

19. A wafer holder according to claim 1, in which the housing is configured to receive a semiconductor wafer with a diameter of 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm), or 12 inches (30.48 cm) or 16 inches (40.72 cm).

20. Use of the wafer holder according to claim 1 for electrochemical porosification of a semiconductor wafer.

21. A method of electrochemical porosification of a semiconductor wafer, comprising the steps of: placing a semiconductor wafer in a wafer holder according to claim 1; immersing the housing in an electrolyte, so that the surface of the semiconductor wafer is exposed to electrolyte through the aperture; and applying a potential difference between the semiconductor wafer and the electrolyte.

22. A method according to claim 21, in which the semiconductor wafer has a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×10.sup.17 cm.sup.−3, beneath a surface layer of a second III-nitride material, having a charge carrier density of less than 1×10.sup.17 cm.sup.−3, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified.

23. A method according to claim 22, in which the surface layer and the sub-surface structure comprise III-nitride materials selected from the list consisting of: GaN, AlGaN, InGaN, InAlN and AlInGaN.

24. A method according to claim 21, comprising the step of photo-electrochemically etching the semiconductor wafer by illuminating the surface of the semiconductor wafer while the potential difference is applied.

25. A porous semiconductor wafer formed by the use of the wafer holder according to claim 20.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Specific embodiments of the invention will now be described with reference to the figures, in which:

[0077] FIG. 1 shows a front view of a wafer holder according to a preferred embodiment of the present invention, with a semiconductor wafer held in the wafer holder;

[0078] FIG. 2 shows a back view of the wafer holder of FIG. 1;

[0079] FIG. 3 is a disassembled view of the wafer holder of FIGS. 1 and 2, showing the reverse side of the front section of the wafer holder;

[0080] FIG. 4 shows the reverse side of the front section of the wafer holder of FIG. 3, with a semiconductor wafer in position;

[0081] FIG. 5 is a disassembled view of the wafer holder of FIGS. 1 and 2, showing the inside of the backing section of the wafer holder;

[0082] FIG. 6 is a schematic illustration of an electrochemical apparatus usable with the present invention;

[0083] FIG. 7 is a photograph showing a semiconductor wafer porosified using the “dipping” technique of the prior art;

[0084] FIG. 8 is a comparative photograph showing a semiconductor wafer porosified using the wafer holder of FIGS. 1 to 5.

[0085] A wafer holder 10 for holding a circular, 4-inch diameter, semiconductor wafer 20 is shown in FIGS. 1 to 5.

[0086] The wafer holder 10 comprises a housing 30 formed from a front section 40 and a backing section 50, which are releasably connectable to one another to assemble and disassemble the housing 30.

[0087] The front section 40 of the housing is ring-shaped, with a circular aperture 60 of 3.5-inch diameter forming an opening through its centre. The outside of the front section 40, which is exposed when the housing is assembled, is formed from acid-resistant plastic. An electrical lead 70 is connected to the front section 40 through an acid-resistant plastic sheath 75. On the reverse (inside) of the front section 40, a metal ring 80 extends around the aperture 60. Six sprung metallic clips 90 are spaced evenly around the metal ring. The metallic clips 90 are electrically connected to the electrical lead 70, so that the metallic clips act as electrical contacts. A first rubber o-ring 100 extends around the aperture 60 inside the diameter of the metal ring 80, and a second rubber o-ring 110 extends around the outside of the metal ring 80.

[0088] The backing section 50 comprises a circular mount 120, around which a third rubber o-ring 130 extends.

[0089] The front section 40 comprises two projections 140 that are keyed to fit two corresponding recesses 150 in the backing section 50, and threaded holes 160 into which bolts 170 may be fitted to connect the front section with the backing section.

[0090] In use, a circular 4-inch semiconductor wafer 20 is placed on the front section 40 as shown in FIG. 4, so that the upper surface of the semiconductor wafer (that is, the surface through which porosification is to proceed) faces the aperture 60. The wafer 20 is aligned with the aperture 60 so that it overlies the first o-ring 100 and contacts all six metallic clips 90. The backing-section is then placed over the wafer 20 so that the third rubber o-ring 130 contacts the bottom surface of the wafer (shown facing upwards in FIG. 4) and the projections 140 are located in the recesses 150. Bolts 170 are then fitted and tightened evenly.

[0091] As the bolts are tightened the front section 40 and the backing section 50 of the housing 30 are squeezed together, so that the semiconductor wafer 20 contacts and compresses both the first and third o-rings to form liquid-tight seals against the wafer, and the metallic clips are forced against the upper surface of the semiconductor wafer 20.

[0092] When the bolts are tightened, the o-rings are compressed so that the housing 30 is sealed against the entry of electrolyte liquid.

[0093] In order to porosify the semiconductor wafer, the wafer holder 10 is immersed in the electrolyte liquid 600 of an electrochemical cell 610 as shown in FIG. 6. A counter electrode 620 is placed in the electrolyte, and a power source 630 is activated so that a potential difference is applied between the counter electrode and the semiconductor wafer. Porosification of the wafer 20 then proceeds as described in WO2019/063957A1.

[0094] In the exemplary embodiment illustrated in FIG. 6, a platinum foil cathode is used as the counter electrode (titanium foil/mesh may alternatively be used), 0.25 M oxalic acid is used as the electrolyte, the power source is a constant DC bias power source, and an ammeter is used to monitor and record the etching current.

[0095] As the upper surface of the wafer 20 is exposed through the aperture 60, but the rest of the wafer is sealed inside the housing 30 and thus is not in contact with the electrolyte, the electrochemical porosification process can proceed only through the upper surface of the semiconductor wafer.

[0096] Although the wafer holder is described above in relation to a 4-inch diameter wafer, the wafer holder may be provided in alternative sizes to fit alternative wafer sizes and shapes.

[0097] Preferably the semiconductor wafer used in the examples is a multi-layered III-nitride semiconductor wafer, in which different layers of the wafer have different charge carrier densities, and are therefore porosified to different extents during etching.

[0098] The structure and composition of the semiconductor wafers, and the control features for the porosification method, are not particular to this invention, as the wafer holder is usable with a large variety of prior art porosifiable semiconductor structures, and with the porosification methods of the prior art, in particular those set out in WO2019/063957A1.

[0099] FIG. 7 shows a 4-inch GaN wafer 700 porosified using the prior art technique of making a single electrical connection to the edge of the wafer, and immersing the wafer by dipping into the electrolyte. Due to the change in refractive index of the semiconductor material caused by porosification, the different colours in the porosified wafer indicate different degrees of porosification at the edges of the wafer compared to the bulk material in the centre of the wafer. Also, at the bottom 710 of the wafer (as shown) where the surface of the electrolyte has been contacting the wafer during porosification, the porosification is uneven.

[0100] FIG. 8 shows a 4-inch GaN wafer 800 with the same structure as that of FIG. 7, which has been mounted in the wafer holder of the present invention during porosification. Due to the o-ring seal around the aperture 60 there is an unporosified border 810 around the perimeter of the wafer, which has been occluded from the electrolyte by the holder during porosification. However, the consistent colour of the central region 820 of the wafer 800 shows that the porosification of this region, which was exposed to electrolyte through the aperture 60, is extremely uniform and consistent. This is attributable, for example, to the even distribution of current around the wafer by the multiple electrical contacts, and to the elimination of “horizontal” etching from the edge of the wafer.