VERTICALLY STRUCTURED POWER TRANSISTOR WITH TRENCH SUPPLY ELECTRODE

Abstract

The invention relates to a vertically structured power transistor, such as a VD-MOS or an IGBT, having a cell comprising: two symmetrical source layers (308), preferably N+ doped, which extend from a front surface (312) of the semiconductor substrate; a well layer (307), preferably P doped, comprising an area having a higher doping concentration (307b) that extends from one source layer to the other; a source/well NP junction (J3) between the source layer and the well layer. According to the invention, a cathode formed on the front surface (312) of the semiconductor substrate has a trench portion (309) with a bottom (313) that extends into the area having a higher doping concentration (307b) of the well layer (307) to a certain depth away from the source/well NP junction (J3).

Claims

1. Power transistor with a vertical structure having a cell exhibiting a plane of symmetry (P1) and comprising a semiconductor support 301, as well as inside the semiconductor support (301): two symmetrical source layers (308), having a first type of conductivity (N.sup.+), starting from a front face (312) of the semiconductor support, said source layers (308) being symmetrical with respect to the plane of symmetry (P1). a body layer (307) having a second type of conductivity (P) opposite to the first type, said body layer comprising an overdoping region (307b) that extends from one source layer (308) to the other, an NP source/body junction (J3) between each source layer (308) and the body layer (307/307b). on the front face (312) of the semiconductor support, a first power supply electrode (302), called cathode, short-circuiting the two source layers (308) and the body layer (307/307b), as well as an insulated control electrode (304), said insulated control electrode (304) being flat, a second power supply electrode (303) called anode, on a rear face (311) of the semiconductor support, the rear face being opposite the front face (312). characterized in that: the cathode has a trench portion (309) formed in an etching (317) arranged in the front face (312) of the semiconductor support between the two source layers (308), said trench cathode portion (309) comprising a base (313) extending into the body layer (307) at a distance depthwise from the NP source/body junction (J3), the overdoping region (307b) extends below the base (313) of the trench cathode portion (309) and at least partially below each source layer (308), the etching (317) has a ratio L.sub.T to L.sub.S (L.sub.T/L.sub.S) here called standard trench length, greater than or equal to 15/20, where L.sub.T denotes half of a maximum dimension of the etching (317) in a transverse direction orthogonal to the plane of symmetry (P1) of the cell and Ls denotes the distance between the plane of symmetry (P1) and the insulated control electrode (304) in the transverse direction.

2. Power transistor according to claim 1, characterized in that the cell also comprises, in the semiconductor support (301): an epitaxial layer (306), of the first type of conductivity, below the body layer (307), and a PN body/epitaxial layer(J2) between the body layer (307) and the epitaxial layer (306). and in that the base (313) of the trench cathode portion (309) extends depthwise at a distance from the PN body/epitaxial junction (J2).

3. Power transistor according to claim 1, characterized in that the trench cathode portion (309) forms an edge (315) in the body layer (307b), at a distance from the NP source/body junction (J3).

4. Power transistor according to claim 1 characterized in that the trench cathode portion (309) has lateral walls (314) that are vertical.

5. Power transistor according to claim 1, characterized in that, for each source layer, the ratio W.sub.T to X.sub.N+ is greater than or equal to 2, where W.sub.T, called depth of trench, denotes a maximum dimension of the etching (317) in a vertical direction, and X.sub.N+, called depth of the source layer, denotes a maximum dimension of the source layer (308) in the vertical direction.

6. Power transistor according to claim 5, characterized in that the ratio W.sub.T to X.sub.N+ is equal to 4.

7. Power transistor according to claim 1, characterized in that, for each source layer (308), the difference between W.sub.T and X.sub.N+ is at least equal to 1 μm, where W.sub.T, called depth of trench, denotes a maximum dimension of the etching (317) in a vertical direction, and X.sub.N+, called depth of the source layer, denotes a maximum dimension of the source layer (308) in the vertical direction.

8. Power transistor according to claim 1, characterized in that W.sub.T=4 μm, L.sub.T=16 μm, X.sub.P+=10 μm, where W.sub.T denotes a maximum dimension of the etching (317) in a vertical direction, L.sub.T denotes half of a maximum length of the etching (317) in the transverse direction, and X.sub.P+ denotes a maximum dimension, in the vertical direction, of the overdoping region (307b) at the level of the etching (317).

9. Power component, characterized in that it comprises a multitude of power transistors according to claim 1, formed on one and the same semiconductor support (301).

Description

[0072] Other details and advantages of the present invention will become apparent on reading the following description, which refers to the attached schematic drawings and relates to a preferred embodiment, given non-limitatively. In these drawings:

[0073] FIG. 1 is a diagrammatic view in vertical cross section of a half-cell of a standard VDMOS of the prior art.

[0074] FIG. 2 is a diagrammatic view in vertical cross section of a half-cell of a standard IGBT of the prior art.

[0075] FIG. 3 is a diagrammatic view in vertical cross section of a half-cell of a power transistor according to the invention.

[0076] FIG. 4 is a graph representing static characteristics, namely the anode current (on the y axis) as a function of the polarization voltage (on the x-axis) for a standard IGBT of the prior art and for various embodiments of an IGBT according to the invention having different values for the trench depth W.sub.T.

[0077] FIG. 5 is a graph representing static characteristics, namely the anode current (on the y axis) as a function of the polarization voltage (on the x-axis) for a standard IGBT of the prior art and for various embodiments of an IGBT according to the invention having different values for the trench length L.sub.T.

[0078] FIG. 6 is a graph representing static characteristics, namely the anode current (on the y axis) as a function of the polarization voltage (on the x-axis) for a standard IGBT of the prior art and for various embodiments of an IGBT according to the invention having different values X.sub.P+ for overdoping below the trench.

[0079] FIG. 7 illustrates the linear energy transfer LET necessary to cause a burn-out for different polarizations and different depths of penetration (“ranges”) for heavy ions originating from the front face of a standard VDMOS (graph on the left (a)) and a VDMOS according to the invention (graph on the right (b)).

[0080] As can be seen in FIG. 3, a power transistor according to the invention comprises a semiconductor support 301 as well as, from the bottom to the top of the figure: [0081] an anode 303 formed by a (metallic) conductive layer arranged on a rear face 311 of the semiconductor support 301, [0082] a substrate 305, which is preferably P.sup.+-doped in the case of an IGBT according to the invention, and which is preferably N.sup.+-doped in the case of a VDMOS according to the invention. [0083] an epitaxial layer 306 preferably weakly N.sup.−-doped, [0084] a body layer 307, preferably P-doped and comprising a P.sup.+ overdoping region referenced 307b, [0085] a source layer 308, preferably heavily N.sup.+-doped, the complete cell thus comprising a second source layer, symmetrical with the layer 308 shown with respect to the plane of symmetry P1; [0086] a control electrode 304 (also called gate) [0087] an insulating layer 316 based on silicon dioxide (SiO.sub.2) for insulating the control electrode 304, [0088] a cathode 302 formed by a metallic conductive layer deposited on a front face 312 of the semiconductor support 301 and over the insulating layer 316. The front face 312 is flat apart from an etching described hereinafter.

[0089] It should be noted that the source layer 308 here extends transversally below the cathode 302 up to the edge of the control electrode 304, i.e. up to the vertical plane P2 that delimits said control electrode 304.

[0090] According to the invention, the cathode 304 has a trench portion 309 that penetrates into the body layer 307, and more specifically into the P.sup.+ overdoping region 307b of the body layer. It will be noted that the trench portion 309 of the cathode is in contact with this P.sup.+ overdoping region 307b over its entire length L.sub.T and over a part of its height W.sub.T. Over the remainder of its height W.sub.T, the trench portion 309 of the cathode is in contact with the N.sup.+ source layer 308.

[0091] In the non-limitative example shown, the trench cathode portion 309 has a vertical section of rectangular shape, with flat, vertical lateral walls 114, and a flat, horizontal base 313. At the intersection of the base 313 and each lateral wall 314, a rectilinear arris 315 can also be observed. The horizontal section of the trench portion 309 of the cathode is also rectangular, preferably square.

[0092] According to the invention, the standardized trench length L.sub.T/Ls is greater than or equal to 15/20 (0.75) and less than 1 by definition. In a preferred version, the standardized trench length L.sub.T/Ls is equal to 16/20. It should be noted furthermore that in FIG. 3, L.sub.N+ denotes the maximum length of each source layer 308, i.e. the maximum dimension of the source layer 308 in the transverse direction.

[0093] The effects of the half-length of the trench L.sub.T can be observed in FIG. 5, which was established with IGBTs according to the invention for which W.sub.T=4 μm, X.sub.P+=9 μm, L.sub.S=20 μm and L.sub.T varies, and with a standard comparable IGBT (trenchless IGBT having the same dimensions apart from the dimensions resulting from the trench). The inventors thus established that with a standardized trench length value of 15/20, the latch-up voltage (anode voltage beyond which latch-up occurs) value is already double with respect to a standard structure and that, for L.sub.T/L.sub.S=16/20, the latch-up phenomenon does not occur at all. In addition, the inventors have shown that the value of the trench half-length L.sub.T has no influence on the value of the threshold voltage of the transistor.

[0094] In the preferred version of the invention, the trench depth W.sub.T is equal to 4 μm. It should be noted that W.sub.T is measured, as shown, between the front face 312 (before metallization) of the semiconductor support taken at the level of the source layer 308 or of the control electrode 304 (=front face of the semiconductor support taken at the level of the etching 317 accommodating the trench cathode portion 309. The inventors have shown that the latch-up phenomena do not occur, regardless of the value for the depth of the trench W.sub.T, as shown in FIG. 4 in the case of an IGBT. Similar results have been obtained for VDMOSs according to the invention which, when subjected to irradiation with heavy ions, no longer suffer burn-out, regardless of the depth of the trench. On the other hand, the value for this depth W.sub.T changes the value of the threshold voltage of the transistor, except for W.sub.T=4 μm in the preferred version of the invention (i.e. with L.sub.T/L.sub.S=16/20); this is why this value will be preferred if it is desired to provide a transistor having static operating characteristics identical to those of the corresponding standard transistor (trenchless transistor having the same dimensions except for the dimensions resulting from the trench, i.e. having the same dimensions L.sub.S, Xn+, L.sub.G, W.sub.N−, W.sub.A, L, etc., where L.sub.G denotes the length of the gate contact in the transverse direction, i.e. the length of the insulated control electrode measured to the end of its oxide layer 316).

[0095] In this preferred version, the depth of overdoping (or of the body) below the trench X.sub.P+, which corresponds to the maximum vertical dimension of the P.sup.+ overdoping region 307b at the level of the trench, is equal to 9 μm. The inventors have shown that the latch-up and burn-out phenomena do not occur when the P/P.sup.+ doping diffusion has a depth of 9 μm or more in the configuration corresponding to the preferred version of the invention (i.e. with the other dimensional values stated in the preceding paragraphs) as shown by the results presented in FIG. 6, established with IGBTs according to the invention for which L.sub.T=16 pm, L.sub.s =20 pm, W.sub.T =4 pm and X.sub.p+varies, and with a standard comparable IGBT (trenchless IGBT having the same dimensions apart from the dimensions resulting from the trench). Now, this value of 9 μm for X.sub.P+ also ensures that the threshold voltage is maintained with respect to a standard structure.

[0096] The inventors have also shown that the proposed trench cathode portion has no influence on the dynamic behaviour of the (VDMOS and IGBT) transistors with respect to the corresponding standard structures. Only a slight reduction in the peak anode current is noted, due to the reduction in the conductive region (region between junction J2 and junction J1) following etching of the trench. In fact, the vertical distance between junctions J1 and J2 reduces with respect to the corresponding transistor of the prior art (trenchless transistor having identical dimensions), since junction J2 is offset downwards by a distance equal to W.sub.T, for an equal X.sub.P+ overdoping depth. If is it desired to retain the same peak current, it is sufficient to “lower” junction J1 in order to retain the distance J1-J2 of the transistor of the prior art, or more generally, to compensate for the loss of conductive surface area.

[0097] In order to obtain the transistor shown in FIG. 3, it is proposed to carry out firstly, the etching 317 by a conventional dry etching process of reactive ion etching (RIE) on a virgin silicon substrate; all the technological steps for a conventional IGBT are then carried out: producing the body 307, including a step of P implantation from the front face 312 with a boron dose that can be 10.sup.16/cm.sup.2 for example; producing the overdosing region 307b around the etching, including a step of P+ implantation from the front face with a boron dose that can be 10.sup.19/cm.sup.2 for example; producing each source layer 308 by N+ implantation from the front face; metallization and opening of the contacts 302, 303.

[0098] It should be noted that, in order to obtain the desired depth of junction at the level of the P+ diffusion (junction J2) at the base of the trench, a fairly long curing time (greater than 5 hours) may be necessary. Furthermore, usually, a step of nitride deposition (Si.sub.3N.sub.4) is carried out before that of opening of the contacts. In order to open the contacts, a dry etching is necessary. However, as the nitride is deposited isotropically, including on the flanks of the trench after etching that is itself anisotropic, insulation may remain on the vertical walls of the trench, severely degrading the quality of the cathode contact. It is therefore preferable to replace this nitride deposition with an oxide that can itself be removed by isotropic wet etching. The oxide can thus be removed from the flanks of the trench.

[0099] The inventors have been able to note that, in a VDMOS according to the invention placed in extreme conditions and in particular bombarded with heavy ions, there is no initiation of the parasitic transistor and therefore no burn-out, regardless of the path of these ions within the substrate and the polarization voltage in the off-state. On the other hand, a standard VDMOS of the prior art is sensitive to all these ions starting from 15% of its breakdown voltage.

[0100] In an IGBT according to the invention, no destructive phenomenon occurs, in the off-state, for a polarization voltage that can reach up to more than 80% of the breakdown voltage. Thus for example, no destructive phenomenon was noted up to a polarization voltage of 500 V (see FIG. 7, where “SEB” signifies “Single Event Burn-out”, i.e. a single destructive event, and where the parameter “R” denotes the “range” i.e. the depth of penetration of the heavy ion into the transistor from the front face), while this same voltage is limited to 90 V in a standard IGBT of the prior art, for one and the same breakdown voltage of 600 V in both structures.

[0101] The invention can be the subject of numerous variants vis-à-vis the preferred embodiment described above, provided that these variants remain within the scope delimited by the attached claims. Thus for example, the form of the trench cathode portion can be different from that illustrated (rectangular cross section) and its dimensions different from those proposed for the preferred version.