ARRAY SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR FABRICATING ARRAY SUBSTRATE

Abstract

An array substrate, a display panel, a display device, and a method for fabricating an array substrate are provided. The array substrate comprises gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, and the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units. Between two of the sub-pixel units which are neighbors in a column direction, at least a portion of the first data line is arranged in a layer different from the neighboring second data line. At least a part of the first data line is arranged in a layer different from that of the neighboring second data line, to overcome the problem of short circuit between dual data lines.

Claims

1. An array substrate, comprising gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, wherein a thin film transistor and a pixel electrode are formed in each of the sub-pixel units, the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units, wherein in every two neighboring columns of sub-pixel units, sub-pixel units in odd rows are connected with the first data line, and sub-pixel units in even rows are connected with the second data line, wherein between two of the sub-pixel units which are neighbors in a column direction, at least a portion of the first data line is arranged in a layer different from the neighboring second data line.

2. The array substrate of claim 1, wherein, the first data line comprises first segments and second segments which are arranged alternately, each first segment and each second segment are arranged in a same layer as a gate of the thin film transistor, and each first segment and an adjacent second segment are electrically connected with each other by a first electrically connecting part; and the second data line is arranged in a same layer as the source and drain of the thin film transistor.

3. The array substrate of claim 2, wherein, each first segment of the first data line is provided with first via holes which are arranged at both ends of each first segment in its extending direction along the first data line, and penetrate a gate insulating layer and a passivation layer of the thin film transistor; each second segment of the first data line is provided with second via holes which are arranged at both ends of the second segment in its extending direction along the first data line, and penetrate the gate insulating layer and the passivation layer; a third via hole is arranged over the source and drain of the thin film transistor and penetrates the passivation layer; and the first electrically connecting part is electrically connected with the source and drain, each first segment of the first data line and the second segment adjacent with the first segment, through the first via holes, the second via holes and the third via hole.

4. The array substrate of claim 2, wherein, the first electrically connecting part is arranged in a same layer as the pixel electrode of each sub-pixel unit.

5. The array substrate of claim 1, wherein, the first data line comprises first segments and second segments which are arranged alternately, the first segments are arranged in a same layer as a source and drain of the thin film transistor, the second segments are arranged in a same layer as a gate of the thin film transistor, and each first segment is electrically connected with an adjacent second segment through a second electrically connecting part.

6. The array substrate of claim 5, wherein, the second data line is arranged in a same layer as the source and drain of the thin film transistor.

7. The array substrate of claim 6, wherein, each first segment of the first data line is provided with fourth via holes which are arranged at both ends of each first segment in its extending direction along the first data line, and penetrate a passivation layer of the thin film transistor; each second segment of the first data line is provided with fifth via holes which are arranged at both ends of the second segment in its extending direction along the first data line, and penetrate a gate insulating layer and the passivation layer; and the second electrically connecting part is electrically connected with each first segment of the first data line and the second segment adjacent with the first segment, through the fourth via holes and the fifth via holes.

8. The array substrate of claim 5, wherein, the second electrically connecting part is arranged in a same layer as the pixel electrode of each sub-pixel unit.

9. The array substrate of claim 6, wherein, the second data line comprises first segments and second segments which are arranged alternately; the first segments of the second data line and the first segments of the first data line are arranged side by side, and are arranged in a same layer as the gate of the thin film transistor; the second segments of the second data line and the second segments of the first data line are arranged side by side, and are arranged in a same layer as the source and drain of the thin film transistor; and the first segments of the second data line are electrically connected with the second segments of the second data line through a third electrically connecting part.

10. The array substrate of claim 9, wherein, each first segment of the second data line is provided with sixth via holes at both ends in its extending direction of the second data line, and the sixth via holes penetrate a gate insulating layer and a passivation layer of the thin film transistor; each second segment of the second data line is provided with seventh via holes at both ends in its extending direction of the second data line, and the seventh via holes penetrate the passivation layer; and the third electrically connecting part electrically connects each first segment of the second data line with the second segment adjacent with the first segment, through the sixth via holes and the seventh via holes.

11. The array substrate of claim 9, wherein, the third electrically connecting part is arranged in a same layer as the pixel electrode of each sub-pixel unit.

12. A display panel, comprising the array substrate of claim 1.

13. A display device, comprising the display panel of claim 12.

14. A method for fabricating an array substrate, wherein the array substrate comprises gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, wherein a thin film transistor and a pixel electrode are formed in each of the sub-pixel units, the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units, wherein in every two neighboring columns of sub-pixel units, sub-pixel units in odd rows are connected with the first data line, and sub-pixel units in even rows are connected with the second data line, wherein the method comprises steps of: forming on a substrate plate a pattern comprising a gate and the gate lines of the thin film transistor and the second segments of the first data line, by a first patterning process; forming a pattern comprising the source and drain of the thin film transistor and the second segments of the second data line by a second patterning process, wherein the second segments of the second data line and the second segments of the first data line are arranged side by side; forming a pattern comprising via holes over the second segments of the first data line and the second segments of the second data line, by a third patterning process; and forming a pattern comprising electrically connecting parts by a fourth patterning process, wherein the electrically connecting parts electrically connect the second segments of the first data line to the adjacent first segments of the first data line.

15. The method of claim 14, by comprising, forming a pattern comprising the gate and the gate lines of the thin film transistor, the second segments of the first data line and the first segments of the first data line, in the first patterning process; and forming a pattern comprising the source and drain of the thin film transistor and a continuous second data line, in the second patterning process.

16. The method of claim 15, comprising, forming a pattern comprising the first via holes, the second via holes, and the third via hole in the third patterning process, wherein the first via holes are arranged at both ends of each first segment of the first data line in its extending direction along the first data line and penetrate a gate insulating layer and a passivation layer of the thin film transistor, the second via holes are arranged at both ends of each second segment of the first data line in its extending direction along the first data line and penetrate the gate insulating layer and the passivation layer, and the third via hole is arranged over a source and drain of the thin film transistor and penetrates the passivation layer; and forming a pattern comprising the first electrically connecting part in the fourth patterning process, wherein the first electrically connecting part is electrically connected with the source and drain, each first segment of the first data line and the second segment adjacent with the first segment, through the first via holes, the second via holes and the third via hole.

17. The method of claim 14, comprising, forming a pattern comprising the source and drain of the thin film transistor, the second segments of the second data line and the first segments of first data line, in the second patterning process.

18. The method of claim 17, comprising, forming a pattern comprising the source and drain of the thin film transistor, the continuous second data line and the first segments of the first data line, in the second patterning process.

19. The method of claim 18, comprising, forming a pattern comprising fourth via holes and fifth via holes in the third patterning process, wherein the fourth via holes are arranged at both ends of each first segment of the first data line in its extending direction along the first data line and penetrate a passivation layer the thin film transistor, and the fifth via holes are arranged at both ends of each second segment of the first data line in its extending direction along the first data line and penetrate the gate insulating layer and the passivation layer; and forming a pattern comprising a second electrically connecting part in the fourth patterning process, wherein the second electrically connecting part is electrically connected with each first segment of the first data line and the second segment adjacent with the first segment, through the fourth via holes and the fifth via holes.

20. The method of claim 17, comprising, forming a pattern comprising the gate and the gate lines of the thin film transistor, the second segments of the first data line and the first segments of the second data line, in the first patterning process.

21-24. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0097] FIG. 1 is a schematic top view illustrating an array substrate in an existing display panel;

[0098] FIG. 2 is a schematic top view illustrating an array substrate in an exemplary embodiment of the present disclosure;

[0099] FIG. 3a and FIG. 3b are schematic cross-sectional views illustrating an array substrate in an exemplary embodiment of the present disclosure, wherein FIG. 3a is a schematic cross-sectional view of the array substrate along a line A-B in FIG. 2, and FIG. 3b is a schematic cross-sectional view of the array substrate along a line C-D in FIG. 2;

[0100] FIG. 4 is a schematic top view illustrating an array substrate in an exemplary embodiment of the present disclosure;

[0101] FIG. 5a and FIG. 5b are schematic cross-sectional views illustrating an array substrate in an exemplary embodiment of the present disclosure, wherein FIG. 5a is a schematic cross-sectional view of the array substrate along a line A-B in FIG. 4, and FIG. 5b is a schematic cross-sectional view of the array substrate along a line C-D in FIG. 4;

[0102] FIG. 6 is a schematic top view illustrating an array substrate in an exemplary embodiment of the present disclosure;

[0103] FIG. 7a, FIG. 7b, FIG. 7c, and FIG. 7d are schematic cross-sectional views illustrating an array substrate in an exemplary embodiment of the present disclosure, wherein FIG. 7a is a schematic cross-sectional view of the array substrate along a line A-B in FIG. 6, FIG. 7b is a schematic cross-sectional view of the array substrate along a line G-H in FIG. 6, FIG. 7c is a schematic cross-sectional view of the array substrate along a line C-D in FIG. 6, and FIG. 7d is a schematic cross-sectional view of the array substrate along a line E-F in FIG. 6;

[0104] FIG. 8a, FIG. 8b, FIG. 8c and FIG. 8d are schematic cross-sectional views illustrating each step for fabricating an array substrate in an exemplary embodiment of the present disclosure; FIG. 9a, FIG. 9b, FIG. 9c, FIG. 9d, and FIG. 9e are schematic cross-sectional views illustrating each step for fabricating an array substrate in an exemplary embodiment of the present disclosure;

[0105] FIG. 10a, FIG. 10b, FIG. 10c, FIG. 10d, FIG. 10e, FIG. 10f, and FIG. 10g are schematic cross-sectional views illustrating each step for fabricating an array substrate in an exemplary embodiment of the present disclosure; and

[0106] FIG. 11a, FIG. 11b, and FIG. 11c are schematic cross-sectional views illustrating each step for fabricating an array substrate in an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0107] Embodiments of the array substrate, the display panel, the display device, and the method for fabricating the array substrate will be described hereinafter by referring to the accompanying drawings. These drawings schematically illustrate structures, portions and/or steps relevant with the inventive concept, and omit or partially illustrate structures, portions and/or steps irrelevant with the inventive concept.

[0108] Reference numerals: 1′ array substrate; 20′ gate line; 30′ sub-pixel unit; 40′ thin film transistor; 40a′ gate; 40b′ source; 40c′ drain; 50′ pixel electrode; 61′ first data line; 62′ second data line; 1, 2, 3 array substrate; 20 gate line; 30 sub-pixel unit; 40 thin film transistor; 40a gate; 40b source; 40c drain; 42 gate insulating layer; 44 passivation layer; 50 pixel electrode; 61 first data line; 62 second data line; 611, 613 first segments of first data line; 612, 614 second segments of first data line; 621 first segments of second data line; 622 second segments of second data line; 701 first via hole; 702 second via hole; 703 third via hole; 704 fourth via hole; 705 fifth via hole; 706 sixth via hole; 707 seventh via hole; 801 first electrically connecting part; 802 second electrically connecting part; 803 third electrically connecting part; 8021 first electrically connecting layer; 8022 second electrically connecting layer; 90, 92 photoresist; 91, 93 mask plate; 911, 931 transparent region, 912, 933 non-transparent region; 932 partially transparent region.

[0109] An array substrate 1 according to an embodiment of the present disclosure will be described hereinafter by referring to FIG. 2, FIG. 3a, and FIG. 3b. FIG. 2 is a schematic top view for the array substrate 1 in the present embodiment, FIG. 3a is a schematic cross-sectional view for the array substrate 1 along a line A-B of FIG. 2, and FIG. 3b is a schematic cross-sectional view for the array substrate 1 along a line C-D of FIG. 2.

[0110] In a display panel, the array substrate 1 comprises gate lines 20 and data lines on a substrate plate 10 which are insulated from each other and intersect to define sub-pixel units 30. In each of the sub-pixel units 30, a thin film transistor 40 and a pixel electrode 50 are formed. The thin film transistor 40 comprises a gate 40a, a source 40b, and a drain 40c. The data lines comprise a first data line 61 and a second data line 62 which are arranged side by side between every two neighboring columns of sub-pixel units 50. In every two neighboring columns of sub-pixel units 30, sub-pixel units 30 in odd rows are connected with the first data line 61, and sub-pixel units in even rows are connected with the second data line 62.

[0111] As shown in FIG. 2, the first data line 61 comprises first segments 611 and second segments 612 which are arranged alternately. Each of the first segments 611 is provided with first via holes 701 at both ends, and each the second segments 612 is provided with second via holes 702 at both ends. A first electrically connecting part 801 electrically connects each of the first segments 611 of the first data line 61 with an adjacent second segment 612 through the first via holes 701 and the second via holes 702. A third via hole 703 is further arranged above the source 40b of the thin film transistor 40. The first electrically connecting part 801 electrically connects both the first segments 611 and the second segments 612 of the first data line 61 to the source 40b of the thin film transistor 40 through the third via hole 703, thus forming a complete first data line 61. The second data line 62 is arranged in a same layer as the source 40b and drain 40c of the thin film transistor 40, and is electrically connected to the source 40b.

[0112] Reference is made to FIG. 3a and FIG. 3b, for describing the first data line 61 and the second data line 62 in details. FIG. 3a is a schematic cross-sectional view for the array substrate 1 along the line A-B in FIG. 2. The line A-B starts at a point A at the pixel electrode 50 of one of the sub-pixel units 30, extends through a portion of one of the first segments 611 of the first data line 61, the first electrically connecting part 801, and a portion of of one the second segments 612 of the first data line 61, and stops at a point B at the pixel electrode 50 of a neighboring sub-pixel unit 30 in the same column. FIG. 3b is a schematic cross-sectional view for the array substrate 1 along the line C-D in FIG. 2. The line C-D starts at a point C at the pixel electrode 50 of one of the sub-pixel units 30, extends through the second data line 62 and the second segments 612 of the first data line 61 in a direction perpendicular to the data line, and stops at a point D at the pixel electrode 50 of a neighboring sub-pixel unit 30 in the same row.

[0113] As shown in FIG. 3a, the first segments 611 and the second segments 612 of the first data line 61, the gate 40a (not shown in FIG. 3a), and the gate lines 20 are arranged on the substrate plate 10. Each of the first segments 611 of the first data line 61 is provided with the first via holes 701 at both ends, and the first via holes 701 penetrate a gate insulating layer 42 and a passivation layer 44 of the thin film transistor 40. The second segments 612 of the first data line 61 is provided with the second via holes 702 at both ends, and the second via holes 702 penetrate the gate insulating layer 42 and the passivation layer 44 of the thin film transistor 40. The third via hole 703 is arranged above the source 40b of the thin film transistor 40 and penetrates the passivation layer 44. The first electrically connecting part 801 is arranged on the passivation layer 44, and electrically connects each of the first segments 611, the adjacent second segment 612, and the source 40b through the first via holes 701, the second via holes 702, and the third via hole 703, thus forming the complete first data line 61.

[0114] As shown in FIG. 3b, the second segments 612 of the first data line 61 is arranged below the gate insulating layer 42 and is arranged in a same layer as the gate 40a (not shown in FIG. 3b), while the second data line 62 is arranged on the gate insulating layer 42 and is arranged in a same layer as the source 40b and the drain 40c (not shown in FIG. 3b). Therefore, the second segments 612 of the first data line 61 is arranged in a layer different from the second data line 62. In addition, as can be seen from FIG. 3a, each of the first segments 611 of the first data line 61 is also arranged in a layer different from the second data line 62.

[0115] Therefore, in the present embodiment, each of the first segments 611 and second segments 612 of the first data line 61 is arranged in a layer different from the second data line 62, so that the DDS problem can be effectively solved. Even in case of a relatively small distance between the first data line 61 and the second data line 62, the first data line and second data line designed as above can effectively solve the DDS problem, so that the yield of product will not be affected adversely.

[0116] As known in the art, a dielectric layer such as planarization layer (not shown) can further be arranged over the passivation layer 44 of the thin film transistor 40. In this case, the first via holes 701, the second via holes 702, and the third via hole 703 accordingly further penetrate the planarization layer.

[0117] An array substrate 2 in an embodiment of the present disclosure will be described hereinafter by referring to FIG. 4, FIG. 5a, and FIG. 5b. FIG. 4 is a schematic top view for the array substrate 2 of the present embodiment, FIG. 5a is a schematic cross-sectional view for the array substrate 2 along a line A-B in FIG. 4, and FIG. 5b is a schematic cross-sectional view for the array substrate 2 along the line C-D in FIG. 4.

[0118] The present embodiment is different from the embodiment shown in FIGS. 2, 3a-3b in that, the first segments of the first data line are arranged in a same layer as the source and drain of the thin film transistor, instead of in a same layer as the gate of the thin film transistor in the embodiment shown in FIGS. 2, 3a-3b.

[0119] As shown in FIG. 4, the first data line 61 comprises first segments 613 and second segments 614 which are arranged alternately. Each of the first segments 613 is provided with fourth via holes 704 at both ends, and each of the second segments 614 is provided with fifth via holes 705 at both ends. A second electrically connecting part 802 electrically connects each of the first segments 613 of the first data line 61 with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61. Since the first segments 613 are arranged in a same layer as the source 40b and drain 40c of the thin film transistor 40, the third via hole 703 in the previous embodiment shown in FIGS. 2, 3a-3b which is arranged above the source 40b can be omitted in this case. The second data line 62 is arranged in a same layer as the source 40b and drain 40c of the thin film transistor 40, and is electrically connected to the source 40b.

[0120] Reference is made to FIG. 5a and FIG. 5b for describing the first data line 61 and the second data line 62 in details.

[0121] As shown in FIG. 5a, the second segments 614 of the first data line 61, the gate 40a (not shown in FIG. 5a), and the gate lines 20 are arranged on the substrate plate 10. The first segments 613 of the first data line 61, and the source 40b and drain 40c of the thin film transistor 40 (not shown in FIG. 5a) are arranged on the gate insulating layer 42. Each of the first segments 613 of the first data line 61 is provided with the fourth via holes 704 at both ends, and the fourth via holes 704 penetrate the passivation layer 44 of the thin film transistor 40. The second segments 614 of the first data line 61 is provided with the fifth via holes 705 at both ends, and the fifth via holes 705 penetrate the gate insulating layer 42 and the passivation layer 44 of the thin film transistor 40. The second electrically connecting part 802 is arranged on the passivation layer 44, and electrically connects each of the first segments 613 with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61.

[0122] As shown in FIG. 5b, the second segments 614 of the first data line 61 is arranged below the gate insulating layer 42 and is arranged in a same layer as the gate 40a (not shown in FIG. 5b), while the second data line 62 is arranged on the gate insulating layer 42 and is arranged in a same layer as the source 40b and the drain 40c (not shown in FIG. 5b). Therefore, the second segments 614 of the first data line 61 is arranged in a layer different from the second data line 62.

[0123] Therefore, in the present embodiment, the second segments 614 of the first data line 61 is arranged in a layer different from the second data line 62, so that the DDS problem can be effectively solved.

[0124] An array substrate 3 in an embodiment of the present disclosure will be described hereinafter by referring to FIG. 6, FIG. 7a, FIG. 7b, FIG. 7c, and FIG. 7d. FIG. 6 is a schematic top view for the array substrate 3 of the present embodiment, FIG. 7a is a schematic cross-sectional view for the array substrate 3 along the line A-B in FIG. 6, FIG. 7b is a schematic cross-sectional view for the array substrate 3 along a line G-H in FIG. 6, FIG. 7c is a schematic cross-sectional view for the array substrate 3 along the line C-D in FIG. 6, and FIG. 7d is a schematic cross-sectional view for the array substrate 3 along a line E-F in FIG. 6.

[0125] The present embodiment is different from the embodiment shown in FIGS. 4, 5a-5b in that the second data line comprises segments which are arranged in a staggered manner, and each of which is arranged in a different layer from the respective segment of the first data line.

[0126] As shown in FIG. 6, the first data line 61 comprises first segments 613 and second segments 614 which are arranged alternately. Each of the first segments 613 is provided with the fourth via holes 704 at both ends, and each of the second segments 614 is provided with the fifth via holes 705 at both ends. The second electrically connecting part 802 electrically connect each of the first segments 613 of the first data line 61 with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61.

[0127] As shown in FIG. 6, the second data line 62 comprises first segments 621 and second segments 622 which are arranged alternately. Each of the first segments 621 is provided with sixth via holes 706 at both ends, and each of the second segments 622 is provided with seventh via holes 707 at both ends. A third electrically connecting part 803 electrically connects each of the first segments 621 of the second data line 62 with the adjacent second segment 622 through the sixth via holes 706 and the seventh via holes 707, thus forming a complete second data line 62.

[0128] Reference is made to FIG. 7a, FIG. 7b, FIG. 7c and FIG. 7d, for describing the first data line 61 and the second data line 62 in details.

[0129] As shown in FIG. 7a, the second segments 614 of the first data line 61, the gate 40a (not shown in FIG. 7a) and gate lines 20 arranged on the substrate plate 10. The first segments 613 of the first data line 61 and the source 40b and drain 40c of the thin film transistor 40 (not shown in FIG. 7a) are arranged on the gate insulating layer 42. The fourth via holes 704 penetrate the passivation layer 44, and the fifth via holes 705 penetrate the gate insulating layer 42 and the passivation layer 44. The second electrically connecting part 802 is arranged on the passivation layer 44, and each of the first segments 613 is electrically connected with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61.

[0130] FIG. 7b is a schematic cross-sectional view for the array substrate 3 along the line G-H in FIG. 6. The line G-H starts at a point G at the pixel electrode 50 of one of the sub-pixel units 30, extends through a portion of one of the second segments 622 of the second data line 62, the third electrically connecting part 803, and a portion of one of the first segments 621 of the second data line 62, and stops at a point H at the pixel electrode 50 of a neighboring sub-pixel unit 30 in the same row. As shown in FIG. 7b, the first segments 621 of the second data line 62, the gate 40a (not shown in FIG. 7b) and gate lines 20 are arranged on the substrate plate 10. The second segments 622 of the second data line 62 and the source 40b and drain 40c of the thin film transistor 40 (not shown in FIG. 7b) are arranged on the gate insulating layer 42. The seventh via holes 707 penetrate the passivation layer 44, and the sixth via holes 706 penetrate the gate insulating layer 42 and the passivation layer 44. The third electrically connecting part 803 is arranged on the passivation layer 44, and electrically connects each of the first segments 621 with the adjacent second segment 622 through the sixth via holes 706 and the seventh via holes 707, thus forming the complete second data line 62.

[0131] As shown in FIG. 7c, the second segments 614 of the first data line 61 are arranged below the gate insulating layer 42 and are arranged in a same layer as the gate 40a (not shown in FIG. 7c), while the second segments 622 of the second data line 62 are arranged on the gate insulating layer 42 and are arranged in a same layer as the source 40b and the drain 40c (not shown in FIG. 7c). Therefore, the second segments 614 of the first data line 61 are arranged in a different layer from the second segments 622 of the second data line 62.

[0132] FIG. 7d is a schematic cross-sectional view for the array substrate 3 along the line E-F in FIG. 6. The line E-F starts at a point Eat the pixel electrode 50 of one of the sub-pixel units 30, extends through the first segments 612 of the second data line 62 and the first segments 613 of the first data line 61 in a direction perpendicular to the data lines, and stops at a point F at the pixel electrode 50 of a neighboring sub-pixel unit 30 in the same column. As shown in FIG. 7d, the first segments 621 of the second data line 62 are arranged below the gate insulating layer 42 and are arranged in a same layer as the gate 40a (not shown in FIG. 7d), while the first segments 613 of the first data line 61 are arranged on the gate insulating layer 42 and are arranged in a same layer as the source 40b and the drain 40c (not shown in FIG. 7d). Therefore, the first segments 613 of the first data line 61 are arranged in a different layer from the first segments 621 of the second data line 62.

[0133] Therefore, in the present embodiment, the first segments 613 of the first data line 61 are arranged in a different layer from the first segments 621 of the second data line 62, and the second segments 614 of the first data line 61 are arranged in a different layer from the second segments 622 of the second data line 62. Namely, any segment of the first data line 61 is arranged in a layer different from a corresponding segment of the second data line 62 which is arranged side by side with respect to the segment of the first data line 61, so that the DDS problem can be effectively solved. Even in case of a relatively small distance between the first data line 61 and the second data line 62, the first data line and the second data line designed as above can effectively solve the DDS problem, so that the yield of product will not be affected adversely.

[0134] A method for fabricating an array substrate according to an embodiment the present disclosure will be described hereinafter by referring to FIG. 8a, FIG. 8b, FIG. 8c, and FIG. 8d. FIGS. 8a-8d are schematic cross-sectional views for illustrating each step for fabricating an array substrate according to the present embodiment.

[0135] In particular, the method for fabricating an array substrate in the present disclosure will be described by taking the array substrate 3 shown in FIGS. 6, 7a-7d as an example. It is noted that each of the cross-sectional views in FIGS. 8a-8d corresponds to the structure along the line A-B in FIG. 6. Namely, FIGS. 8a-8d only illustrate each step for fabricating the first data line 61.

[0136] Firstly, a pattern comprising the gate 40a and the gate lines 20 of the thin film transistor 40, the second segments 614 of the first data line 61 (FIG. 8a) and the first segments 621 of the second data line 62 (FIG. 7d) is formed on the substrate plate 10 by a first patterning process.

[0137] Then, the gate insulating layer 42 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the source 40b and drain 40c of the thin film transistor 40, the first segments 613 of the first data line 61 (FIG. 8b), and the second segments 622 of the second data line 62 (FIG. 7c) is formed by a second patterning process.

[0138] Then, the passivation layer 44 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the fourth via holes 704 and the fifth via holes 705 (FIG. 8c and FIG. 7a) as well as the sixth via holes 706 and the seventh via holes 707 (FIG. 7b) is formed by a third patterning process. The fourth via holes 704 are arranged at both ends of each of the first segments 613 of the first data line 61, and penetrate the passivation layer 44 to expose a portion of each of the first segments 613. The fifth via holes 705 are arranged at both ends of each of the second segments 614 of the first data line 61, and penetrate the gate insulating layer 42 and the passivation layer 44 to expose a portion of each of the second segments 614. The sixth via holes 706 are arranged at both ends of each of the first segments 621 of the second data line 62, and penetrate the gate insulating layer 42 and the passivation layer 44 to expose a portion of each of the first segments 621. The seventh via holes 707 are arranged at both ends of each of the second segments 622 of the second data line 62, and penetrate the passivation layer 44 to expose a portion of each of the second segments 622.

[0139] Finally, a pattern comprising the second electrically connecting part 802 (FIG. 8d) and third electrically connecting part 803 (FIG. 7b) is formed on the resulting substrate plate 10 from the previous step by a fourth patterning process. The second electrically connecting part 802 electrically connects each of the first segments 613 of the first data line 61 with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61. The third electrically connecting part 803 electrically connects each of the first segments 621 of the second data line 62 with the adjacent second segment 622 through the sixth via holes 706 and the seventh via holes 707, thus forming the complete second data line 62.

[0140] Through the above steps, the fabrication of the first data line 61 and the second data line 62 is complete, and the array substrate 3 shown in FIGS. 6, 7a-7d is obtained.

[0141] In an implementation, as shown in FIG. 8d, in the fourth patterning process, during forming the second electrically connecting part 802 and the third electrically connecting part 803, a pattern of the pixel electrode 50 in each of the sub-pixel units 30 is formed at the same time.

[0142] A method for fabricating the array substrate 1 shown in FIG. 2, FIGS. 3a-3b will be described hereinafter.

[0143] Firstly, a pattern comprising the gate 40a and the gate lines 20 of the thin film transistor 40, the first segments 611 of the first data line 61, and the second segments 612 of the first data line 61 is formed on the substrate plate 10 by a first patterning process (FIG. 3a).

[0144] Then, the gate insulating layer 42 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the source 40b and drain 40c of the thin film transistor 40 and the second data line 62 is formed by a second patterning process (FIG. 3b).

[0145] Then, the passivation layer 44 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the first via holes 701, the second via holes 703, and the third via hole 703 is formed by a third patterning process (FIG. 3a). The first via holes 701 are arranged at both ends of each of the first segments 611 of the first data line 61, and penetrate the gate insulating layer 42 and the passivation layer 44 to expose a portion of each of the first segments 611. The second via holes 702 are arranged at both ends of the second segments 612 of the first data line 61, and penetrate the gate insulating layer 42 and the passivation layer 44 to expose a portion of each of the first segments 612. The third via hole 703 is arranged above the source 40b of the thin film transistor 40, and penetrates the passivation layer 44 to expose a portion of the source 40b.

[0146] Finally, a pattern comprising the first electrically connecting part 801 is formed on the resulting substrate plate 10 from the previous step by a fourth patterning process (FIG. 3a). The first electrically connecting part 801 electrically connects each of the first segments 611, the adjacent second segment 612, and the source 40b through the first via holes 701, the second via holes 702, and the third via hole 703, thus forming the complete first data line 61.

[0147] Through the above steps, the fabrication of the first data line 61 and the second data line 62 is complete, and the array substrate 1 shown in FIGS. 2, 3a-3b is obtained.

[0148] A method for fabricating the array substrate 2 shown in FIG. 4, FIG. 5a-5b will be described hereinafter.

[0149] Firstly, a pattern comprising the gate 40a and the gate lines 20 of the thin film transistor 40 and the second segments 614 of the first data line 61 is formed on the substrate plate 10 by a first patterning process (FIG. 5a).

[0150] Then, the gate insulating layer 42 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the source 40b and drain 40c of the thin film transistor 40, the first segments 613 of the first data line 61, and the second data line 62 is formed by a second patterning process (FIG. 5b).

[0151] Then, the passivation layer 44 is deposited on the resulting substrate plate 10 from the previous step, and a pattern comprising the fourth via holes 704 and the fifth via holes 705 is formed by a third patterning process (FIG. 5a). The fourth via holes 704 are arranged at both ends of the first segments 613 of the first data line 61, and penetrate the passivation layer 44 to expose a portion of each of the first segments 613. The fifth via holes 705 are arranged at both ends of the second segments 614 of the first data line 61, and penetrate the gate insulating layer 42 and the passivation layer 44 to expose a portion of each of the first segments 614.

[0152] Finally, a pattern comprising the second electrically connecting part 802 is formed on the resulting substrate plate 10 from the previous step by a fourth patterning process (FIG. 5a). The second electrically connecting part 802 electrically connects the first segments 613 of the first data line 61 with the adjacent second segment 614 through the fourth via holes 704 and the fifth via holes 705, thus forming the complete first data line 61.

[0153] Through the above steps, the fabrication of the first data line 61 and the second data line 62 is complete, and the array substrate 2 shown in FIGS. 4, 5a-5b is obtained.

[0154] A method for fabricating an array substrate according to an embodiment of the present disclosure will be described hereinafter by referring to FIGS. 9a-9e. FIGS. 9a-9e are schematic cross-sectional views illustrating each step for fabricating an array substrate according to the present embodiment.

[0155] In particular, the fourth patterning process shown in FIG. 8d will be described in the present embodiment in details. In the fourth patterning process, a pattern comprising the electrically connecting parts and the pixel electrode of each of the sub-pixel units is formed, and the electrically connecting parts and the pixel electrode are made from a same material. For example, steps for forming the second electrically connecting part 802 and the pixel electrode 50 in the fourth patterning process will be described by taking the embodiment shown in FIG. 6 and FIG. 7a as an example.

[0156] Firstly, as shown in FIG. 9a, a first electrically connecting layer 8021 is deposited on the resulting substrate plate 10 from the third patterning process shown in FIG. 8c. The first electrically connecting layer 8021 can be made from a conductive material from which the pixel electrode 50 is made. For example, the conductive material can be ITO. The conductive material can further be other transparent conductive oxides such as IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), and InGaSnO (indium gallium tin oxide). Of course, the pixel electrode 50 can also be made from other conductive materials.

[0157] Then, as shown in FIG. 9b, photoresist 90 is applied on the substrate plate 10. An exposure process is conducted with a mask plate 91. The mask plate 91 comprises a transparent region 911 and a non-transparent region 912. The non-transparent region 912 corresponds to a region on the substrate plate 10 where the pixel electrode 50 and the second electrically connecting part 802 are to be formed, while the transparent region 911 corresponds to a remaining region on the substrate plate 10. After exposure, the photoresist 90 in the region where the pixel electrode 50 and the second electrically connecting part 802 are to be formed is retained, and the photoresist 90 in the remaining region is removed to expose the first electrically connecting layer 8021, as shown in FIG. 9c.

[0158] Then, as shown in FIG. 9d, the first electrically connecting layer 8021 is removed by etching in the remaining region.

[0159] Finally, as shown in FIG. 9e, the photoresist 90 in the region where the pixel electrode 50 and the second electrically connecting part 802 are to be formed is stripped, thus forming the second electrically connecting part 802 and the pixel electrode 50.

[0160] Through the above steps, the second electrically connecting part 802 and the pixel electrode 50 which is formed from the first electrically connecting layer 8021 are formed. The first electrically connecting layer 8021 is made from ITO.

[0161] According to the present embodiment, in the patterning process for forming the pixel electrode 50, the second electrically connecting part 802 is formed at the same. In this manner, no patterning process is added in the existing fabricating process, and thus the cost is not increased.

[0162] A method for fabricating an array substrate according to an embodiment of the present disclosure will be described hereinafter by referring to FIG. 10a, FIG. 10b, FIG. 10c, FIG. 10d, FIG. 10e, FIG. 10f, and FIG. 10g. FIGS. 10a-10g are schematic cross-sectional views illustrating each step for fabricating an array substrate according to the present embodiment.

[0163] The present embodiment differs from the embodiment shown in FIGS. 9a-9e in that, apart from a same material as the pixel electrode, the electrically connecting parts further comprise a metal layer. Namely, the electrically connecting parts comprise stacked layers of a first electrically connecting layer and a second electrically connecting layer, wherein the first electrically connecting layer is ITO, and the second electrically connecting layer is a metal. Steps for forming the second electrically connecting part 802 and the pixel electrode 50 in the fourth patterning process will be described, by still taking the embodiment shown in FIG. 6 and FIG. 7a as an example.

[0164] Firstly, as shown in FIG. 10a, the first electrically connecting layer 8021 and second electrically connecting layer 8022 are deposited in sequence on the resulting substrate plate 10 from the third patterning process shown in FIG. 8c. The first electrically connecting layer 8021 can be made from a conductive material from which the pixel electrode 50 is formed. For example, the conductive material can be ITO. The second electrically connecting layer 8022 can comprise a metal.

[0165] As shown in FIG. 10b, photoresist 92 is applied on the substrate plate 10. An exposure process is conducted with a mask plate 93. The mask plate 93 is a translucent mask plate, for example a half-tone mask plate and a gray-tone mask plate. The mask plate 93 comprises a transparent region 931, a partially transparent region 932, and a non-transparent region 933. The non-transparent region 933 corresponds to a region on the substrate plate 10 where the second electrically connecting part 802 is to be formed, the partially transparent region 932 corresponds to a region on the substrate plate 10 where the pixel electrode 50 is to be formed, while the transparent region 931 corresponds to a remaining region on the substrate plate 10.

[0166] As shown in FIG. 10c, after exposure, the photoresist 92 in the region where the second electrically connecting part 802 is to be formed is completely retained, the photoresist 92 in the region where the pixel electrode 50 is to be formed is partially retained, and the photoresist 92 in the remaining region is completely removed. In the remaining region, since the photoresist 92 is removed, the second electrically connecting layer 8022 is exposed.

[0167] As shown in FIG. 10d, in the remaining region, the second electrically connecting layer 8022 is removed by dry etching to expose the first electrically connecting layer 8021, and the first electrically connecting layer 8021 is removed by etching.

[0168] As shown in FIG. 10e, the photoresist 92 in the region where the pixel electrode 50 is to be formed is removed by ashing, thus exposing the second electrically connecting layer 8022. During ashing, the photoresist 92 in the region where the second electrically connecting part 802 is to be formed is thinned.

[0169] As shown in FIG. 10f, in the region where the pixel electrode 50 is to be formed, the second electrically connecting layer 8022 is removed by dry etching, and the first electrically connecting layer 8021 is retained to form the pixel electrode 50.

[0170] Finally, as shown in FIG. 10g, the photoresist 92 in the region where the second electrically connecting part 802 is to be formed is stripped, and the second electrically connecting part 802 consisting of the first electrically connecting layer 8021 and the second electrically connecting layer 8022 is formed.

[0171] Through the above steps, the pixel electrode 50 consisting of the first electrically connecting layer 8021 is formed, and the second electrically connecting part 802 consisting of the first electrically connecting layer 8021 and the second electrically connecting layer 8022 is formed. The first electrically connecting layer 8021 can be made from ITO. the second electrically connecting layer 8022 can be made from a metal, for example Mo, Cu, Mg, Ca, Cr, W, Ti, Ta, or the like.

[0172] In the present embodiment, since the second electrically connecting part 802 is formed by stacked layers of the first electrically connecting layer 8021 and the second electrically connecting layer 8022, a translucent mask plate such as the half-tone mask plate and the gray-tone mask plate is adopted in the exposure step.

[0173] In a step corresponding to the cross-sectional view of FIG. 10f, the second electrically connecting layer 8022 in the region where the pixel electrode 50 is to be formed is removed dry etching. Therefore, the method of this embodiment is particularly applicable to a case in which the second electrically connecting layer 8022 of the second electrically connecting part 802 does not comprise Al.

[0174] A method for fabricating an array substrate according to an embodiment of the present disclosure will be described hereinafter by referring to FIG. 11a, FIG. 11b, and FIG. 11c. FIGS. 11a-11c are schematic cross-sectional views for illustrating each step for fabricating an array substrate according to the present embodiment.

[0175] The present embodiment differs from the embodiment shown in FIGS. 10a-10g in that, the second electrically connecting layer 8022 of the second electrically connecting part 802 comprises Al. Steps for forming the second electrically connecting part 802 and the pixel electrode 50 in the fourth patterning process will be described, by still taking the embodiment shown in FIG. 6 and FIG. 7a as an example.

[0176] In the present embodiment, since the second electrically connecting layer 8022 comprises metal Al, the second electrically connecting layer 8022 in the region where the pixel electrode 50 is to be formed is for example removed by wet etching in the step corresponding to the cross-sectional view of FIG. 10f. Namely, the present embodiment differs from the embodiment shown in FIGS. 10a-10g in the step of removing the second electrically connecting layer 8022 which comprises Al in the region where the pixel electrode 50 is to be formed.

[0177] As shown by open arrows in FIG. 11a, the first electrically connecting layer 8021 on the substrate plate 10 shown in FIG. 10e is annealed, to improve crystalline quality of the conductive material e.g., of ITO, thus improving its etching resistance.

[0178] As shown in FIG. 11b, the second electrically connecting layer 8022 in the region where the pixel electrode 50 is to be formed is removed by wet etching. During the wet etching, since the first electrically connecting layer 8021 is subject to annealing treatment in advance, ITO in the first electrically connecting layer 8021 is resistant to etching of a solution for the wet etching. This facilitates ensuring performance of the pixel electrode 50 to be formed.

[0179] Finally, as shown in FIG. 11c, the photoresist 92 in the region where the second electrically connecting part 802 is to be formed is stripped, thus forming the second electrically connecting part 802 consisting of the first electrically connecting layer 8021 and the second electrically connecting layer 8022.

[0180] Through the above steps, the pixel electrode 50 made from the first electrically connecting layer 8021 is formed, and the second electrically connecting part 802 made from the first electrically connecting layer 8021 and the second electrically connecting layer 8022 is formed. The first electrically connecting layer 8021 can be made from ITO. the second electrically connecting layer 8022 comprises Al.

[0181] Alternatively, in case the second electrically connecting layer 8022 comprises Al, it is possible not to anneal the first electrically connecting layer 8021 in advance, but to select an appropriate etching solution and etching time, so as to reduce adverse effect of the etching solution on ITO in the first electrically connecting layer 8021 as much as possible. As shown in FIGS. 11a-11c, the second electrically connecting layer 8022 for example comprises stacked metal layers. Namely, the second electrically connecting layer 8022 can comprise a single metal layer or stacked metal layers of low electrical resistivity, thus improving conductivity of the second electrically connecting part 802. In this manner, excellent electrically connection between the first segments 613 and the second segments 614 of the first data line 61 is facilitated. For example, the second electrically connecting layer 8022 can comprise a single Mo layer, or comprise stacked Mo/Al/Mo layers. Alternatively, the second electrically connecting layer can comprise two, four, or more metal layers.

[0182] In the above embodiments described with reference to FIGS. 9a-9e, FIGS. 10a-10g, and FIGS. 11a-11c, the electrically connecting parts in the present disclosure have been described by taking the second electrically connecting part 802 as an example. It is noted that the above description also applies to the first electrically connecting part 801 and the third electrically connecting part 803.

[0183] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel. The display panel comprises the array substrate as described in the above embodiments of the present disclosure. The display panel further comprises other essential parts, which are known for a person with ordinary skill in the art, so that they are not described herein for simplicity and are not considered as limitations to the present disclosure.

[0184] The present embodiment further provides a display device. The display device comprises the display panel as described above. The display device can be any product or component with display function, for example a mobile phone, a tablet computer, a TV set, a monitor, a notebook computer, a digital photo frame, and a navigator.

[0185] According to the present disclosure, at least a part of the first data line is arranged in a layer different from that of the neighboring second data line. In this manner, DDS can be effectively prevented, thus improving the yield of product. Cross-talk between dual data lines which are arranged side by side can be significantly eliminated, thus improving the display quality of product. In addition, a small distance between dual data lines can be realized, thus improving the aperture ratio and wiring density of the array substrate. For example, some segments of the first data line are arranged in a same layer as the gate of the thin film transistor, and the corresponding portions of the second data line which are arranged side by side with respect to these segments are arranged in a same layer as the source and drain of the thin film transistor. As a result, these segments of the first data line and the corresponding portions of the second data line are arranged in different layers, so that the first data line and the second data line are at least partially arranged in different layers, thus preventing short circuit and cross-talk between dual data lines which are arranged side by side. According to technical solutions of the present disclosure, there is no addition to patterning processes in the existing fabricating process, thus leading no increase in cost.

[0186] The foregoing descriptions of embodiments of the present disclosure have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit this disclosure. Accordingly, many modifications and variations will be apparent to the person with ordinary skill in the art. For example, in the above embodiments, a portion of the second data line is arranged in a same layer as the source and drain, and a corresponding portion of the first data line which is arranged side by side with respect to the portion of the second data line is arranged in a same layer as the gate, so that the first data line is at least partially arranged in a different layer from the second data line, thus alleviating or eliminating DDS. However, the present disclosure does not intend to restrict a layer in which the portion of the first data line lies and a different layer in which the portion of the second data line lies. For example, apart from the layer in which the source and the drain lie and the layer in which the gate lies as described above, The corresponding portion of the first data line can also be arranged in other conductive layers in the array substrate. These conductive layers can not only be existing conductive layers in the array substrate, but also additional conductive layers which are added intentionally. In addition, in the above embodiments, via holes in each segment of the data lines are arranged close to the gate lines of the thin film transistor, and the electrically connecting parts are arranged across the gate lines to electrically connect neighboring segments with each other, so as to form a complete first data line and/or second data line. However, the present disclosure does not intend to restrict positions of the electrically connecting parts and positions of via holes in each segment. For example, segments of the first data line and/or second data line can be arranged across the gate lines and the electrically connecting parts can be arranged between two neighboring gate lines, provided that the segments are electrically connected with each other by the electrically connecting parts to form a complete data line. In short, the scope of the present disclosure is defined by the appended claims.