SEMICONDUCTOR STORAGE DEVICE

Abstract

A semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate, transistors, a first interconnect, and first bonding electrodes. The second chip includes a memory cell array and second bonding electrodes. The second bonding electrodes are bonded to the first bonding electrodes. The first chip or the second chip has bonding pad electrodes. The second bonding electrodes include third bonding electrodes and fourth bonding electrodes. The third and fourth bonding electrodes overlap the memory cell array. The third bonding electrodes are in a current pathway between the memory cell array and the transistors whereas the fourth bonding electrodes are not in such a current pathway. The first interconnect is electrically connected to a bonding pad electrode and a fourth bonding electrode directly, without a current path via any one of transistors.

Claims

1. A semiconductor storage device, comprising: a first chip including a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes; a second chip including a memory cell array and a plurality of second bonding electrodes, the second bonding electrodes being bonded to the first bonding electrodes; and a plurality of bonding pad electrodes on the first chip or the second chip, the bonding pad electrodes being connectable to bonding wires, wherein the plurality of second bonding electrodes includes: third bonding electrodes that overlap the memory cell array and are in a current pathway between the memory cell array and the transistors; and fourth bonding electrodes that overlap the memory cell array but are not in a current pathway between the memory cell array and the transistors, the first interconnect is electrically connected to a bonding pad electrode in the plurality of bonding pad electrodes without via any of the transistors being in the electrical connection between the bonding pad electrode and the first interconnect, and the first interconnect is electrically connected to a fourth bonding electrode in the plurality of fourth bonding electrodes without any of the transistors being in the electrical connection between the fourth bonding electrode and the first interconnect.

2. The semiconductor storage device according to claim 1, wherein the bonding pad electrode is a first bonding pad electrode connected to a ground voltage.

3. The semiconductor storage device according to claim 2, wherein the plurality of bonding pad electrodes includes: a second bonding pad electrode for supply of a driving voltage higher than the ground voltage; and a third bonding pad electrode for supply of a signal.

4. The semiconductor storage device according to claim 1, wherein the first chip further comprises a plurality of interconnect layers, and the first interconnect is at least one of the interconnect layers.

5. The semiconductor storage device according to claim 4, wherein the first interconnect is the interconnect layer in the plurality that is nearest to the semiconductor substrate.

6. The semiconductor storage device according to claim 4, further comprising: a first contact electrode electrically connecting the first interconnect to the semiconductor substrate.

7. The semiconductor storage device according to claim 4, further comprising: a first electrode between the first interconnect and the semiconductor substrate; and a contact electrode electrically connecting the first interconnect and the first electrode.

8. A semiconductor storage device, comprising: a first chip including a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes; a second chip including a memory cell array and a plurality of second bonding electrodes bonded to the first bonding electrodes; and a plurality of bonding pad electrodes on the first chip or the second chip, the bonding pad electrodes being connectable to bonding wires, wherein the plurality of second bonding electrodes includes: a plurality of third bonding electrodes that do not overlap the memory cell array but do overlap one of the bonding pad electrodes; and a plurality of fourth bonding electrodes that do not overlap either the memory cell or any one of the bonding pad electrodes, the first interconnect is electrically connected to one of the bonding pad electrodes in the plurality of bonding pad electrodes without via any of the transistors being in the electrical connection between the one of the bonding pad electrodes and the first interconnect, and the first interconnect is electrically connected to and a fourth bonding electrodes in the plurality of fourth bonding electrodes without via any of the transistors being in the electrical connection between the fourth bonding electrode and the first interconnect.

9. The semiconductor storage device according to claim 8, wherein the one of the bonding pad electrodes is a first bonding pad electrode for supply of a ground voltage.

10. The semiconductor storage device according to claim 9, wherein the plurality of bonding pad electrodes includes: a second bonding pad electrode for supply of a driving voltage higher than the ground voltage; and a third bonding pad electrode for supply of a signal.

11. The semiconductor storage device according to claim 8, wherein the first chip comprises a plurality of interconnect layers, and the first interconnect is at least one of the interconnect layers.

12. The semiconductor storage device according to claim 11, wherein the first interconnect is the interconnect layer nearest to the semiconductor substrate.

13. The semiconductor storage device according to claim 11, further comprising: a first contact electrode electrically connecting the first interconnect and the semiconductor substrate.

14. The semiconductor storage device according to claim 11, further comprising: a first electrode between the first interconnect and the semiconductor substrate; and a contact electrode electrically connecting the first interconnect and the first electrode.

15. A semiconductor storage device, comprising: a first chip including a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes; a second chip including a memory cell array and a plurality of second bonding electrodes bonded to the first bonding electrodes; and a plurality of bonding pad electrodes on at least one of the first chip or the second chip, the bonding pad electrodes being connectable to bonding wires, wherein the first interconnect is electrically connected to a bonding pad electrode in the plurality of bonding pad electrodes without via any of the transistors being in the electrical connection between the bonding pad electrode and the first interconnect, and the first interconnect is electrically connected to a at least one of the first bonding electrodes or at least one of the second bonding electrodes without any of the transistors being in the electrical connection between the at least one of the first bonding electrodes or the at least one of the second bonding electrodes.

16. The semiconductor storage device according to claim 15, wherein the one of the bonding pad electrodes is a first bonding pad electrode for supply of a ground voltage.

17. The semiconductor storage device according to claim 16, wherein the plurality of bonding pad electrodes includes: a second bonding pad electrode for supply of a driving voltage higher than the ground voltage; and a third bonding pad electrode for supply of a signal.

18. The semiconductor storage device according to claim 15, wherein the first chip comprises a plurality of interconnect layers, and the first interconnect comprises the interconnect layer in the nearest to the semiconductor substrate.

19. The semiconductor storage device according to claim 18, further comprising: a first contact electrode electrically connecting the first interconnect and the semiconductor substrate.

20. The semiconductor storage device according to claim 18, further comprising: a first electrode between the first interconnect and the semiconductor substrate; and a contact electrode electrically connecting the first interconnect and the first electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a schematic block diagram of an example configuration of a memory system 10 according to a first embodiment.

[0005] FIG. 2 depicts an example configuration of a memory system in a schematic side view according to a first embodiment.

[0006] FIG. 3 depicts an example configuration of a memory system in a schematic plan view according to a first embodiment.

[0007] FIG. 4 depicts an example configuration of a memory die in a schematic perspective view according to a first embodiment.

[0008] FIG. 5 depicts an example configuration of a chip in a memory die in a schematic bottom view according to a first embodiment.

[0009] FIG. 6 depicts an example configuration of a chip in a memory die in a schematic bottom view according to a first embodiment.

[0010] FIG. 7 depicts an example configuration of a chip in a memory die in a schematic plan view according to a first embodiment.

[0011] FIG. 8 depicts an example configuration of a memory die corresponding to line A-A′ of FIG. 6 in a schematic cross-sectional view according to a first embodiment.

[0012] FIG. 9 depicts an example configuration of a memory die corresponding to line B-B′ of FIG. 6 in a schematic cross-sectional view according to a first embodiment.

[0013] FIG. 10 depicts an example configuration of a memory die in a schematic enlarged view according to a first embodiment.

[0014] FIG. 11 depicts an example configuration of a memory die in a schematic cross-sectional view according to a first embodiment.

[0015] FIG. 12 depicts an example configuration of a chip in a memory die in a schematic plan view according to a first embodiment.

[0016] FIG. 13 depicts an example configuration of a chip in a memory die in a schematic cross-sectional view according to a first embodiment.

[0017] FIG. 14 depicts an example configuration of a chip in a memory die in a schematic cross-sectional view according to a first embodiment.

[0018] FIG. 15 is a schematic circuit diagram of an example configuration of a memory die according to a first embodiment.

[0019] FIG. 16 is a schematic circuit diagram of an example configuration of a memory die according to a first embodiment.

[0020] FIG. 17 is a schematic circuit diagram of an example configuration of a memory die according to a first embodiment.

[0021] FIG. 18 depicts an example configuration of a memory die in a schematic cross-sectional view according to a first embodiment.

[0022] FIG. 19 depicts an example configuration of a memory die in a schematic cross-sectional view according to a first embodiment.

DETAILED DESCRIPTION

[0023] Embodiments provide a semiconductor storage device which operates at high speed.

[0024] According to one embodiment, a semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes. The second chip including a memory cell array and a plurality of second bonding electrodes. The second bonding electrodes are bonded to the first bonding electrodes. At least one of the first chip and the second chip has a plurality of bonding pad electrodes connectable to bonding wires. The second bonding electrodes comprise a plurality of third bonding electrodes and a plurality of fourth bonding electrodes. Both the third and fourth bonding electrodes overlap the memory cell array when viewed in a direction intersecting a surface of the semiconductor substrate. The third bonding electrodes are in a current pathway between the memory cell array and the transistors whereas the fourth bonding electrodes are not in such a current pathway. The first interconnect is electrically connected to one of the bonding pad electrodes without via any of the transistors being in the current path, and the first interconnect is also electrically connected to at least one of the fourth bonding electrodes without via any of the transistors being in the current path.

[0025] Certain non-limiting example embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawings are schematic and as such some components or elements may be omitted for convenience of illustration. In general, the same reference symbols are used throughout the drawings and description of aspects or elements previously described in conjunction with a drawing may be omitted from the discussion a description thereof is sometimes omitted.

[0026] Herein, the term “semiconductor storage device” may refer to a memory die, a memory system including a controller die, such as a memory chip, a memory card or a Solid-State Drive (SSD), and/or a host computer, such as a smartphone, a tablet computer or a personal computer, incorporating a memory system or memory die.

[0027] The phrase “a first component is electrically connected to a second component can be used to describe a case where the first component is connected directly to the second component and a case where the first component is connected to the second component via a semiconductor member or a transistor. For example, when three transistors are connected in series with each other, the first transistor can be said to be electrically connected to the third transistor even when the second transistor is in an off state.

[0028] As used herein, the phrase “a first component is connected between a second component and a third component” includes a case where the first component, the second component, and the third component are connected in series with each other, and the second component may be connected to the third component via the first component.

[0029] As used herein, the phrase “a circuit conducts electricity between two interconnects” includes a case where the circuit includes, for example, a transistor in a current pathway between the two interconnects, and the transistor turns on (is in an on state).

[0030] As used herein, the X direction refers to a direction parallel to the upper surface of a substrate, the Y direction refers to a direction parallel to the upper surface of the substrate and perpendicular to the X direction, and the Z direction refers to a direction orthogonal to the upper surface of the substrate.

[0031] As used herein, the first direction refers to a direction along a given plane, the second direction refers to another direction along the given plane intersecting with the first direction, and the third direction refers to a direction intersecting the given plane. The first direction, the second direction, and the third direction may or may not correspond to the X direction, the Y direction, and the Z direction.

[0032] As used herein, such expressions as “upper” and “lower” are based on distance from a semiconductor substrate. For example, the direction going away from the semiconductor substrate along the Z direction is referred to as “upward” or the like, while the direction approaching to the semiconductor substrate along the Z direction is referred to as “downward” or “lower”. A first component farther from the semiconductor substrate than a second component may be said to be “above” the second component, and the second component may be said to be “below” the first component. The lower surface or the lower end of a component refers to the semiconductor substrate facing side or end of the component, while the upper surface or the upper end of the component refers to the opposite surface or end of the component. A surface intersecting the X direction or the Y direction can be referred to as a side surface or the like.

First Embodiment

[0033] Memory System 10

[0034] FIG. 1 is a schematic block diagram of an example configuration of a memory system 10 according to a first embodiment.

[0035] The memory system 10 performs reading, writing, erasing, etc. of user data in response to a signal transmitted from a host computer 20. The memory system 10 is, for example, a system that can memorize user data, such as a memory chip, a memory card, or an SSD. The memory system 10 includes a plurality of memory dies MD and a controller die CD. The controller die CD is connected to the memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, a RAM, etc. and performs processing, such as translation between logical address and physical address, detection/correction of bit error, garbage correction (or compaction), and wear leveling.

[0036] FIG. 2 depicts, in a schematic side view, an example configuration of the memory system 10 of the first embodiment. FIG. 3 depicts, in a schematic plan view, an example configuration of the memory system 10 of the first embodiment.

[0037] As shown in FIGS. 2 and 3, the memory system 10 of the first embodiment further includes a mounting substrate MSB, on which the memory dies MD are stacked in layers. The controller die CD is mounted on the uppermost memory die MD. Each of the mounting substrate MSB, the memory dies MD, and the controller die D has a plurality of bonding pad electrodes P.sub.X. The bonding pad electrodes P.sub.X in each layer are disposed on a Y-direction end area of an exposed upper surface and aligned with each other in X-direction. For example, while a part of the upper surface of the mounting substrate MSB is bonded, for example with an adhesive, to a lower surface of the lowermost memory die MD, the bonding pad electrodes P.sub.X are provided to the Y-direction end area of the exposed upper surface of the mounting substrate MSB, that is the surface not bonded to the lowermost memory die MD. In a similar manner, while a part of the upper surface of each of the memory dies MD is bonded, for example with an adhesive, to a lower surface of another memory die MD in an upper layer, the bonding pad electrodes P.sub.X are provided to the Y-direction end area of the exposed upper surface of each layer. The uppermost memory die MD is bonded to a lower surface of the controller CD, that is the top layer of the stacking structure of the memory system 10 in the present embodiment, and the Y-direction end area of the upper surface of the controller die CD has the bonding pad electrodes P.sub.X exposed thereon.

[0038] As shown in FIG. 3, the bonding pad electrodes P.sub.X of the mounting substrate MSB, the bonding pad electrodes P.sub.X of each memory die MD, and the bonding pad electrodes P.sub.X of the controller die CD are connected to each other by bonding wires B.

[0039] The configuration shown in FIGS. 2 and 3 is one example and may be modified as appropriate or as needed. For example, in the configuration of FIGS. 2 and 3, the controller die CD in the top layer is mounted on the uppermost memory die MD, and these components are electrically connected to each other by the bonding wires B. In one instance, the memory dies MD and the controller die CD having such a configuration are incorporated in one package. In another instance, the controller die CD and the memory dies MD may be incorporated in separate packages. The memory dies MD and the controller die CD may be bonded not by the bonding wires B but by, for example, through-vias.

[0040] Configuration of Memory Die MD

[0041] FIG. 4 depicts, in a schematic exploded perspective view, an example configuration of the memory die MD of the first embodiment. As shown in FIG. 4, the memory die MD includes a chip C.sub.M having a memory cell array MCA (see, for example, FIG. 8) and a chip C.sub.P having a peripheral circuit.

[0042] The bonding pad electrodes P.sub.X are provided on an upper surface of the chip C.sub.M. A plurality of bonding electrodes P.sub.I1 are provided on a lower surface of the chip C.sub.M. A plurality of bonding electrodes P.sub.I2 are provided on an upper surface of the chip C.sub.P. Herein, for the chip C.sub.M, the upper surface on which the bonding electrodes P.sub.I1 are provided may also be referred to as a front surface of the chip C.sub.M, while the lower surface on which the bonding pad electrodes P.sub.X are provided may also be referred to as a back surface of the chip C.sub.M. For the chip C.sub.P, the upper surface on which the bonding electrodes P.sub.I2 are provided may also be referred to as a front surface of the chip C.sub.P, while a lower surface on the side opposite to the front surface may also be referred to as a back surface of the chip C.sub.P. In the example of FIG. 4, the front surface of the chip C.sub.P is positioned above the back surface of the chip C.sub.P, and the back surface of the chip C.sub.M is positioned above the front surface of the chip C.sub.M.

[0043] The chip C.sub.M and the chip C.sub.P are disposed such that the front surface of the chip C.sub.M and the front surface of the chip C.sub.P face each other. The bonding electrodes P.sub.I1 are provided at positions corresponding to the bonding electrodes P.sub.I2 so that they can be bonded to the bonding electrodes P.sub.I2. The bonding electrodes P.sub.I1 and the bonding electrodes P.sub.I2 function as bonding electrodes for bonding and electrically connecting the chip C.sub.M and the chip C.sub.P together. The bonding pad electrodes P.sub.X function as the pad electrodes (see FIGS. 2 and 3).

[0044] The corners a1, a2, a3, and a4 of the chip C.sub.M correspond to the corners b1, b2, b3, and b4 of the chip C.sub.P, respectively.

[0045] FIG. 5 depicts, in a schematic bottom view, an example configuration of the chip C.sub.M. FIG. 6 depicts, in a schematic bottom view, an example configuration of an inside of the chip C.sub.M viewed from the chip surface on which the bonding electrodes P.sub.I1 are provided. FIG. 7 depicts, in a schematic plan view, an example configuration of the chip C.sub.P. FIG. 8 depicts, in a schematic cross-sectional view, an example configuration of the memory die MD corresponding to the line A-A′ of FIG. 6. FIG. 9 depicts, in a schematic cross-sectional view, an example configuration of the memory die MD corresponding to the line B-B′ of FIG. 6. FIG. 10 depicts, in a schematic enlarged view, an example configuration of a portion of the memory die of FIG. 9.

[0046] Structure of Chip C.sub.M

[0047] As shown in FIG. 6, the chip C.sub.M has four memory cell array regions R.sub.MCA arranged in the X and Y directions. Each memory cell array region R.sub.MCA includes a memory hole region R.sub.MH, in which memory cells are provided, and hookup regions R.sub.HU provided on both sides (for example, left and right sides in FIG. 6) of the memory hole region R.sub.MH in the X direction. The chip C.sub.M also has a peripheral region R.sub.P outside the four memory cell array regions R.sub.MCA. The peripheral region R.sub.P includes a region between the two memory cell array regions R.sub.MCA in the Y direction, regions between the memory cell array regions R.sub.MCA and the Y-direction ends of the chip C.sub.M, and regions between the memory cell array regions R.sub.MCA and the X-direction ends of the chip C.sub.M. Input/output circuit regions R.sub.IO are provided in the peripheral region R.sub.P at positions corresponding to the bonding pad electrodes P.sub.X that are provided as shown in FIGS. 2, 3 and 4.

[0048] While the hookup regions RHO are provided on both sides in the X direction of each memory hole region R.sub.MH in the present embodiment, this configuration is one example and may be modified as appropriate or as needed. For example, the hookup region (or regions) R.sub.HU may be provided at or near the center in the X direction of each memory cell array region R.sub.MCA.

[0049] As shown in FIGS. 8 and 9, the chip C.sub.M includes a substrate layer L.sub.SB, a memory cell array layer L.sub.MCA provided below the substrate layer L.sub.SB, and interconnect layers 140, 150, and 160 provided below the memory cell array layer L.sub.MCA.

[0050] Structure of the Substrate Layer L.sub.SB of Chip C.sub.M

[0051] As shown in FIG. 8, the substrate layer L.sub.SB includes a semiconductor layer 100, an insulating layer 101 provided on an upper surface of the semiconductor layer 100, and an insulating layer 102 provided on an upper surface of the insulating layer 101. As shown in FIG. 9, the bonding pad electrodes P.sub.X are disposed between the insulating layer 101 and the insulating layer 102 and provided in the input/output circuit regions R.sub.IO.

[0052] The semiconductor layer 100 is formed of, for example, silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B). A layer of a metal such as tungsten (W) or a silicide such as tungsten silicide (WSi) may be provided between the semiconductor layer 100 and the insulating layer 101. The semiconductor layer 100 is provided in a plurality of regions which are separated from each other in the X and Y directions. For example, the semiconductor layer 100 is provided in four regions corresponding to the four memory cell array regions R.sub.MCA that are shown in FIG. 6.

[0053] The insulating layer 101 is formed of, for example, an insulating material such as silicon oxide (SiO.sub.2). As shown in FIGS. 8 and 9, the insulating layer 101 entirely covers the upper surface and side surfaces of the semiconductor layer 100 and also an upper surface of an insulating layer 103 contained in the memory cell array layer L.sub.MCA. The insulating layer 103 is formed of, for example, silicon oxide (SiO.sub.2).

[0054] The insulating layer 102 may be a passivation layer formed of an insulating material such as polyimide.

[0055] The bonding pad electrodes P.sub.X comprise a conductive material such as aluminum (Al). As shown in FIG. 9, the bonding pad electrodes P.sub.X each include an external connection region 104 and an internal connection region 105. The external connection region 104 is provided on the upper surface of the semiconductor layer 100 via the insulating layer 101. The internal connection region 105 is provided on the upper surface of the insulating layer 103 contained in the memory cell array layer L.sub.MCA.

[0056] The external connection region 104 is connected to the bonding wires B that are arranged as shown in FIGS. 2 and 3. An opening is provided at least in part of an area of the insulating layer 102 which corresponds to the external connection region 104. The external connection region 104 is exposed from the opening to the outside of the memory die MD.

[0057] The internal connection region 105 is connected to contacts 112 contained in the memory cell array layer L.sub.MCA. The internal connection region 105 is provided below the external connection region 104.

[0058] Structure of the Memory Cell Array Layer L.sub.MCA of Chip C.sub.M

[0059] As shown in FIG. 9, the memory cell array MCA is provided in each memory cell array region R.sub.MCA in the memory cell array layer L.sub.MCA. The memory cell array MCA includes a plurality of memory blocks BLK and a plurality of inter-block insulating layers 106. The memory blocks BLK are arranged in the Y direction. Each of the inter-block insulating layers 106 is formed of, for example, silicon oxide (SiO.sub.2) and provided between the memory blocks BLK.

[0060] Each memory block BLK contained in the memory hole region R.sub.MH includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the conductive layers 110 and the semiconductor layers 120. The gate insulating films 130 are separately and partially shown in FIG. 10.

[0061] As shown in FIG. 8, the conductive layers 110 each have a plate-like or substantially plate-like shape extending in the X direction. Each conductive layer 110 may comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is, for example, formed of tungsten (W). Alternatively, each conductive layer 110 may comprise, for example, polycrystalline silicon containing an impurity such as phosphorus (P) or boron (B). Insulating films 111 formed of, for example, silicon oxide (SiO.sub.2) are provided between the conductive layers 110 arranged in the Z direction. The conductive layers 110 function, for example, as gate electrodes of word lines and memory cells connected to the word lines.

[0062] The semiconductor layers 120 function, for example, as channel regions of memory cells. The semiconductor layers 120 are formed of, for example, polycrystalline silicon (Si). Each semiconductor layer 120 has, for example, a cylindrical or substantially cylindrical shape. A peripheral surface of each semiconductor layer 120 is covered with and faces the conductive layers 110.

[0063] Each semiconductor layer 120, at a lower end thereof, has an impurity region (not separately depicted) containing an N-type impurity such as phosphorus (P). The impurity region is connected to a bit line BL via a contact 121 and a contact 122.

[0064] Each semiconductor layer 120, at an upper end thereof, has an impurity region (not separately depicted) containing an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B). The impurity region is connected to the semiconductor layer 100.

[0065] The gate insulating films 130 each have a cylindrical or substantially cylindrical shape that covers the peripheral surface of the semiconductor layer 120. As shown in FIG. 10, each gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133, which are stacked between the semiconductor layer 120 and the conductive layers 110. Each of the tunnel insulating film 131 and the block insulating film 133 is, for example, formed of silicon oxide (SiO.sub.2). The charge storage film 132 is, for example, formed of silicon nitride (Si.sub.3N.sub.4) and is capable of storing charges. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 each have a cylindrical or substantially cylindrical shape and extend in the Z direction along the peripheral surface of the semiconductor layer 120.

[0066] The gate insulating film 130 may include, instead of the charge storage film 132, a floating gate formed of, for example, polycrystalline silicon containing an N-type or P-type impurity.

[0067] As shown in FIG. 8, each memory block BLK has the X-direction ends of its conductive layers 110 arranged in the hookup region R.sub.HU along the Z direction and the contacts 112 extending in the Z direction.

[0068] The conductive layers 110 have ends arranged in a stair-like or substantially stair-like structure in the hookup region R.sub.HU. Thus, the X-direction end of a lower one of the conductive layers 110 is positioned nearer to the memory hole region R.sub.MH, and the X-direction end of an upper one of the conductive layers 110 is positioned farther from the memory hole region R.sub.MH.

[0069] Each contact 112 comprises, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, tungsten (W). Each contact 112 has, for example, a cylindrical or substantially cylindrical shape. The contacts 112, at upper ends thereof, are connected to different conductive layers 110 and, at lower ends thereof, are connected to different interconnects 141.

[0070] As shown in FIG. 9, the input/output circuit regions R.sub.IO of the memory cell array layer L.sub.MCA each include the plurality of contacts 112 extending in the Z direction. The contacts 112 are connected to, at upper ends thereof, a lower surface of the internal connection region 105 of the bonding pad electrode P.sub.X and are, at lower ends thereof, connected to the respective interconnects 141.

[0071] Structures of the Interconnect Layers 140, 150, 160 of Chip C.sub.M

[0072] The interconnects in the interconnect layers 140, 150, and 160 are, in one instance, electrically connected to at least one of components or structures in the memory cell array layer L.sub.MCA or at least one of components or structures in the chip C.sub.P. In another instance, the interconnects are electrically connected to both the components or structures in the memory cell array layer L.sub.MCA and the components or structures in the chip C.sub.P.

[0073] The interconnect layer 140 includes a plurality of interconnects 141. The interconnects 141 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu). Some of the interconnects 141 function as bit lines BL. As an example, the bit lines BL are arranged in the X direction as shown in FIG. 8 and extend in the Y direction as shown in FIG. 9. The bit lines BL are connected to the semiconductor layers 120.

[0074] The interconnect layer 150 includes a plurality of interconnects 151. The interconnects 151 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0075] The interconnect layer 160 includes a plurality or a set of bonding electrodes P.sub.I1. The bonding electrodes P.sub.I1 of the interconnect layer 160 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0076] As shown in FIG. 5, another set of bonding electrodes P.sub.I1 are provided in each hookup region R.sub.HU. The bonding electrodes P.sub.I1 of the hookup region R.sub.HU are electrically connected to the conductive layers 110 via the contacts 112 (see FIG. 8).

[0077] As shown in FIG. 5, each memory hole region R.sub.MH includes a region R1 and a region R2. The region R1 overlaps a sense amplifier module region R.sub.SAM (see FIG. 7) when viewed in the Z direction. The region R2 does not overlap the sense amplifier module region R.sub.SAM (see FIG. 7) when viewed in the Z direction.

[0078] As shown in FIG. 5, still another set of bonding electrodes P.sub.I1 are provided in the region R1. The bonding electrodes P.sub.I1 of the region R1 are electrically connected to the bit lines BL (see FIG. 8).

[0079] As shown in FIG. 5, a further set of bonding electrodes P.sub.I1 are provided in the region R2.

[0080] As shown in FIG. 5, a still further set of bonding electrodes P.sub.I1 are provided in each input/output circuit region R.sub.IO. The bonding electrodes P.sub.I1 of the input/output circuit region R.sub.IO are electrically connected to the bonding pad electrode P.sub.X via the contacts 112 (see FIG. 9).

[0081] As shown in FIG. 5, another set of bonding electrodes P.sub.I1 are provided in an area of the peripheral region R.sub.P lying outside the input/output circuit regions R.sub.IO.

[0082] Structure of Chip C.sub.P

[0083] As shown in FIG. 7, the chip C.sub.P has four circuit regions R.sub.PC provided at positions corresponding to the four memory cell array regions R.sub.MCA (that are arranged as shown in FIG. 6). Each circuit region R.sub.PC includes a sense amplifier module region R.sub.SAM provided at a position corresponding to part of the memory hole region R.sub.MH (FIG. 6), and two row decoder regions R.sub.RD provided at positions corresponding to the two hookup regions R.sub.HU (FIG. 6). The chip C.sub.P also has its own peripheral region and input/output circuit regions R.sub.IO. The peripheral region R.sub.P of the chip C.sub.P is provided at a position corresponding to the peripheral region R.sub.P of the chip C.sub.M. The input/output circuit regions R.sub.IO of the chip C.sub.P are provided at positions corresponding to the input/output circuit regions R.sub.IO of the chip C.sub.M.

[0084] As shown in FIGS. 8 and 9, the chip C.sub.P includes a semiconductor substrate 200, a transistor layer L.sub.TR provided above the semiconductor substrate 200, and interconnect layers 220, 230, 240, and 250 provided above the transistor layer L.sub.TR.

[0085] Structure of the Semiconductor Substrate 200 of Chip C.sub.P

[0086] The semiconductor substrate 200 is formed of, for example, P-type silicon (Si) containing a P-type impurity such as boron (B). A semiconductor substrate region 200S and an insulating region 2001 are provided in a surface of the semiconductor substrate 200.

[0087] Structure of the Transistor Layer L.sub.TR of Chip C.sub.P

[0088] In the transistor layer L.sub.TR, an electrode layer 210 is provided on an upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer 210 includes a plurality of electrodes 211 that face the surface of the semiconductor substrate 200. The electrodes 211 of the electrode layer 210 and respective regions of the semiconductor substrate 200 are connected to contacts 201.

[0089] The semiconductor substrate region 200S of the semiconductor substrate 200 functions as, for example, a channel region of transistors Tr constituting a peripheral circuit.

[0090] The electrodes 211 of the electrode layer 210 function as, for example, gate electrodes of the transistors Tr constituting the peripheral circuit. Each electrode 211 comprises, for example, a semiconductor layer and a metal layer provided on an upper surface of the semiconductor layer. The semiconductor layer is formed of, for example, polycrystalline silicon (Si) containing an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B). The metal layer is formed of, for example, tungsten (W).

[0091] The contacts 201 extend in the Z direction and, at their lower ends, are connected to the upper surface of the semiconductor substrate 200 or the upper surfaces of the electrodes 211. Each contact 201 may comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, tungsten (W).

[0092] The transistors Tr provided on the semiconductor substrate 200 each constitute part of the peripheral circuit.

[0093] For example, the transistors Tr provided in the row decoder regions R.sub.RD (see FIG. 7) constitute part of a row decoder which transfers a voltage selectively to one of the conductive layers 110. Some of the transistors Tr constituting the row decoder function as word-line switches which are connected to the conductive layers 110 without using any other transistors Tr.

[0094] The transistors Tr provided in the sense amplifier module regions R.sub.SAM (see FIG. 7) constitute part of a sense amplifier module which measures a voltage or electric current of the bit lines BL and transfers a voltage selectively to one of the bit lines BL. Some of the transistors Tr constituting the sense amplifier module function as bit-line switches which are connected to the bit lines BL without using any other transistors Tr.

[0095] The transistors Tr provided in the input/output circuit regions R.sub.IO (see FIG. 7) function as an input/output circuit which performs input/output of user data, command data or address data via some of the bonding pad electrodes P.sub.X. Some of the transistors Tr constituting the input/output circuit function as part of a pull-up circuit, part of a pull-down circuit, or part of a comparator which is connected to the bonding pad electrodes P.sub.X without using any other transistors Tr.

[0096] Structures of the Interconnect Layers 220, 230, 240, and 250 of Chip C.sub.P

[0097] The interconnects in the interconnect layers 220, 230, 240, and 250 are, in one instance, electrically connected to at least one of components or structures in the transistor layer L.sub.TR or at least one of components or structures in the chip C.sub.M. In another instance, the interconnects are electrically connected to both the components or structures in the memory cell array layer L.sub.TR and the components or structures in the chip C.sub.M.

[0098] The interconnect layer 220 includes a plurality of interconnects 221. The interconnects 221 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0099] The interconnect layer 230 includes a plurality of interconnects 231. The interconnects 231 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0100] The interconnect layer 240 includes a plurality of interconnects 241. The interconnects 241 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0101] The interconnect layer 250 includes a plurality or a set of bonding electrodes P.sub.I2. The bonding electrodes P.sub.I2 of the interconnect layer 250 may each comprise, for example, a stacked film consisting of a barrier conductive film and a metal film. The barrier conductive film is formed of, for example, titanium nitride (TiN). The metal film is formed of, for example, copper (Cu).

[0102] As shown in FIG. 7, another set of bonding electrodes P.sub.I2 are provided in each row decoder region R.sub.RD. The bonding electrodes P.sub.I2 of the row decoder regions R.sub.RD are electrically connected to the transistors Tr, which constitute the row decoder, via the contacts 201 provided in the transistor layer L.sub.TR as shown in FIG. 9. Further, the bonding electrodes P.sub.I2 of the row decoder regions R.sub.RD are electrically connected to the conductive layers 110 via the bonding electrodes P.sub.I1.

[0103] As shown in FIG. 7, still another set of bonding electrodes P.sub.I2 are provided in each sense amplifier module region R.sub.SAM. The bonding electrodes P.sub.I2 of the sense amplifier module regions R.sub.SAM are electrically connected to the transistors Tr, which constitute the sense amplifier module, via the contacts 201 provided in the transistor layer L.sub.TR as shown in FIG. 9. Further, the bonding electrodes P.sub.I2 of the sense amplifier module regions R.sub.SAM are electrically connected to the bit lines BL via the bonding electrodes P.sub.I1.

[0104] As shown in FIG. 7, a further set of bonding electrodes P.sub.I2 are provided in a region R3 which is located in each circuit region R.sub.PC and which overlaps the region R2 arranged as shown in FIG. 5, when viewed in the Z direction.

[0105] As shown in FIG. 7, a still further set of bonding electrodes P.sub.I2 are provided in each input/output circuit region R.sub.IO. The bonding electrodes P.sub.I2 of the input/output circuit regions R.sub.IO are electrically connected to the transistors Tr, which constitute the input/output circuit, via the contacts 201 arranged as shown in FIG. 9. The bonding electrodes P.sub.I2 of the input/output circuit regions R.sub.IO are also electrically connected to the bonding pad electrodes P.sub.X via the bonding electrodes P.sub.I1.

[0106] As shown in FIG. 7, another set of bonding electrodes P.sub.I2 are provided in an area of the peripheral region R.sub.P lying outside the input/output circuit regions R.sub.IO.

[0107] Heat Dissipation Structure of Memory Die MD

[0108] When a read operation, a write operation, an erasing operation, or the like is performed on the memory die MD, the transistors Tr in the chip C.sub.P generate heat. Temperatures of the respective transistors Tr may be monitored and controlled to be at a predetermined temperature or lower. When the temperatures reach a predetermined threshold value, an operation speed of the memory die MD may have to be reduced.

[0109] Generally, it is difficult for a memory die MD to operate at a high speed for a long time due to rising temperatures resulting from prolonged high-speed operations.

[0110] The memory die MD of the present embodiment has a heat dissipation structure for efficiently dissipating the heat of the transistors Tr outside the memory die MD. As shown in FIG. 11, the heat dissipation structure includes an interconnect m.sub.T provided in the vicinity of the transistors Tr, a bonding pad electrode P.sub.XT electrically connected to the interconnect m.sub.T without using any transistors Tr in the memory die MD, and bonding electrodes P.sub.I1T and P.sub.I2T electrically connected to the interconnect m.sub.T without using any transistors Tr in the memory die MD.

[0111] The heat dissipation structure enables the heat generated by the transistors Tr to be absorbed by the nearby interconnect m.sub.T and dissipated outside the memory system 10 via the bonding pad electrode P.sub.XT and further through the bonding wires B (see FIGS. 2 and 3).

[0112] The bonding electrodes P.sub.I1T, P.sub.I2T may comprise a material having a relatively excellent heat absorbing properties, such as copper (Cu), and have a relatively large volume. With such bonding electrodes, the heat dissipation structure can further efficiently absorb the heat generated by the transistors Tr.

[0113] Interconnect m.sub.T

[0114] The interconnect m.sub.T may be one of the interconnects 221.

[0115] The interconnect m.sub.T may be provided in the vicinity of a transistor Tr which generates a relatively large amount of heat. Such a transistor Tr may, for example, constitute a charge pump circuit C.sub.CP or an input/output circuit C.sub.IO (see FIG. 12). In one instance, the transistor Tr constituting the charge pump circuit C.sub.CP may be provided, for example, in the region R3 as shown in FIG. 12. In that case, the interconnect m.sub.T may be provided in the region R3. In another instance, the transistor Tr constituting the charge pump circuit C.sub.CP may be provided, for example, in an area of the peripheral region R.sub.P lying outside the input/output circuit regions R.sub.IO as shown in FIG. 12. In that case, the interconnect m.sub.T may be provided in such an area. The transistor Tr constituting the input/output circuit C.sub.IO may be provided, for example, in the input/output circuit region R.sub.IO as shown in FIG. 12. In that case, the interconnect m.sub.T may be provided in the input/output circuit region R.sub.IO.

[0116] As shown in FIG. 13, the interconnect m.sub.T may be connected to the semiconductor substrate region 200S of the semiconductor substrate 200 via the contact 201. Such a region on the semiconductor substrate region 200S may be, for example, a region that does not function as part of the transistor Tr.

[0117] As shown in FIG. 14, the interconnect m.sub.T may be connected to one of the electrodes 211. Such an electrode 211 may be an electrode that does not function as part of the transistor Tr.

[0118] Such a configuration as illustrated in FIG. 13 or 14 can substantially reduce a distance between the interconnect m.sub.T and the transistor Tr. Further, since the semiconductor substrate 200 conducts heat, the heat generated by the transistor Tr can be absorbed also via the semiconductor substrate 200. This enables more efficient absorption of the heat.

[0119] Bonding Pad Electrode P.sub.XT

[0120] Referring back to FIG. 11, the bonding pad electrode P.sub.XT may be one of the bonding pad electrodes P.sub.X.

[0121] The bonding pad electrodes P.sub.X include, for example, bonding pad electrodes used for supply of a grounding voltage, bonding pad electrodes used for supply of an operating voltage which is higher than the grounding voltage, bonding pad electrodes used for input of data or a signal such as a clock signal, bonding pad electrodes used for control of the memory die MD, and the like. The bonding pad electrode P.sub.XT is, for example, one of the bonding pad electrodes P.sub.X used for the grounding voltage supply.

[0122] Bonding Electrodes P.sub.I1T and P.sub.I2T

[0123] The bonding electrodes P.sub.I1T and P.sub.I2T may be some of the bonding electrodes P.sub.I1 and P.sub.I2.

[0124] As shown in FIG. 5, the bonding electrodes P.sub.I1 are provided on the front surface of the chip C.sub.M. As shown in FIG. 7, the bonding electrodes P.sub.I2 are provided on the front surface of the chip C.sub.P. Some of the bonding electrodes P.sub.I1, P.sub.I2 are provided in a current pathway (may also be referred to as a first current pathway herein) between the transistor Tr and the component (e.g., the conductive layer 110, the bit line BL, or the semiconductor layer 100) in the memory cell array MCA (see, for example, FIG. 8). Further, some of the bonding electrodes P.sub.I1 and P.sub.I2 are provided in a current pathway (may also be referred to as a second current pathway herein) between the bonding pad electrode P.sub.X and the transistor Tr (see, for example. FIG. 9). In the present embodiment, at least some of the bonding electrodes P.sub.I1 and P.sub.I2 other than the bonding electrodes P.sub.I1 and P.sub.I2 provided in the first and second current pathways are used as the bonding electrodes P.sub.I1T and P.sub.I2T (see, for example, FIG. 11).

[0125] The bonding electrodes P.sub.I1 used as the bonding electrodes P.sub.I1T are, for example, at least some of the bonding electrodes P.sub.I1 provided in the regions R2 of FIG. 5 or at least some of the bonding electrodes P.sub.I1 provided in the area of the peripheral region R.sub.P lying outside the input/output circuit regions R.sub.IO.

[0126] The bonding electrodes P.sub.I1T and P.sub.I2T used as the bonding electrodes P.sub.I2T are, for example, at least some of the bonding electrodes P.sub.I2 provided in the regions R3 of FIG. 7 or at least some of the bonding electrodes P.sub.I2 provided in the area of the peripheral region R.sub.P lying outside the input/output circuit regions R.sub.IO.

[0127] The bonding electrodes P.sub.I1T and P.sub.I2T are electrically connected to the interconnect m.sub.T and the bonding pad electrode P.sub.XT without using any transistors Tr in the memory die MD as shown in FIG. 11.

[0128] At least some of the bonding electrodes P.sub.I1T, P.sub.I2T may be provided in a current pathway (may also be referred to as a third current pathway herein) between the interconnect m.sub.T and the bonding pad electrode P.sub.XT as shown in FIG. 15.

[0129] In this case, as shown in FIGS. 11 and 15, a lower end of a contact electrode may be connected to an upper surface of at least one of the bonding electrodes P.sub.I1T, and via this contact electrode, the bonding electrode P.sub.I1T may be electrically connected to some of the interconnects 141 and 151. Further, an upper end of another contact electrode may be connected to a lower surface of the bonding electrode P.sub.I2T, and via this contact electrode, the bonding electrode P.sub.I2T may be electrically connected to some of the interconnects 231 and 241. The bonding electrode P.sub.I2T is bonded to the bonding electrode P.sub.I1T.

[0130] At least some of the bonding electrodes PUT, P.sub.I2T may not be provided in the third current pathway between the interconnect m.sub.T and the bonding pad electrode P.sub.XT as shown in FIG. 16 or 17.

[0131] In this case, as shown in FIGS. 16 and 18, the contact electrode connected to the upper surface of at least one of the bonding electrodes P.sub.I1T in the configuration of FIGS. 11 and 15 may be omitted. For example, the bonding electrode P.sub.I1T in the memory hole region R.sub.MH in FIG. 18 does not have the contact electrode connected to the upper surface thereof. On the other hand, in a similar manner to the configuration of FIGS. 11 and 15, the bonding electrode P.sub.I2T may be electrically connected to some of the interconnects 231 and 241 via another contact electrode connected to the lower surface of the bonding electrode P.sub.I2T.

[0132] Alternatively, as shown in FIGS. 17 and 19, the contact electrode connected to the lower surface of the bonding electrode P.sub.I2T in the configuration of FIGS. 11 and 15 may be omitted. For example, the bonding electrodes P.sub.I2T in the memory hole region R.sub.SAM in FIG. 19 do not have the contact electrode connected to the lower surface thereof. On the other hand, in a similar manner to the configuration of FIGS. 11 and 15, the bonding electrode P.sub.I1T may be electrically connected to some of the interconnects 141 and 151 via another contact electrode connected to the upper surface of the bonding electrode P.sub.I1T.

Other Embodiments

[0133] The configuration according to the first embodiment is one example and may be modified as appropriate or as needed.

[0134] For example, in the first embodiment, the chip C.sub.M has the three interconnect layers 140, 150, and 160, and the chip C.sub.P has the four interconnect layers 220, 230, 240, and 250. This configuration is one example and may be modified. For example, the chip C.sub.M may have four or more interconnect layers, and the chip C.sub.P may have five or more interconnect layers.

[0135] In the first embodiment, the bonding pad electrodes P.sub.X are provided in the chip C.sub.M having the memory cell array MCA. This configuration is one example and may be modified. For example, the bonding pad electrodes P.sub.X may be provided in the chip C.sub.P having the peripheral circuit.

[0136] While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.