Flash Memory Array With Individual Memory Cell Read, Program And Erase

Abstract

A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Claims

1. A memory device, comprising: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells; and each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells.

2. The memory device of claim 1, wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

3. The memory device of claim 1, wherein: the memory cells are arranged in pairs of the memory cells; and each of the pairs of memory cells shares one of the source regions and one of the source lines.

4. The memory device of claim 1, wherein for each of the memory cells, the control gate comprises a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

5. A memory device, comprising: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the columns of memory cells includes a source line that electrically connects together all the source regions for the column of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; and each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells.

6. The memory device of claim 5, wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

7. The memory device of claim 5, wherein: the memory cells are arranged in pairs of the memory cells; and each of the pairs of memory cells shares one of the source regions and one of the source lines.

8. The memory device of claim 5, wherein for each of the memory cells, the control gate comprises a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

9. A memory device, comprising: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, a control gate disposed over and insulated from the floating gate, a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and an erase gate disposed over and insulated from the source region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells.

10. The memory device of claim 9, wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

11. The memory device of claim 9, wherein: the memory cells are arranged in pairs of the memory cells; and each of the pairs of memory cells shares one of the source regions and one of the source lines.

12. The memory device of claim 11, wherein each of the pairs of memory cells shares one of the erase gates and one of the erase gate lines.

13. A method of erasing a selected memory cell of a memory device, wherein the memory device comprises: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows, and wherein one of the plurality of memory cells is a selected memory cell; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells; and each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells; the method comprising: applying a positive voltage to one of the first or second control gate lines that is electrically connected to the control gate of the selected memory cell, and a ground voltage to all the others of the first and second control gate lines; applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines; and applying a ground voltage to all of the bit lines.

14. The method of claim 13, wherein the positive voltage applied to the one of the first or second control gate lines is greater than the positive voltage applied to the others of the source lines.

15. The method of claim 13, wherein the positive voltage applied to the one of the first or second control gate lines is at least double than that of the positive voltage applied to the others of the source lines.

16. A method of erasing a selected memory cell of a memory device, wherein the memory device comprises: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein one of the plurality of memory cells is a selected memory cell; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the columns of memory cells includes a source line that electrically connects together all the source regions for the column of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; and each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells; the method comprising: applying a positive voltage to one of the control gate lines that is electrically connected to the control gate of the selected memory cell, and a ground voltage to all the others of the control gate lines; applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines; and applying a ground voltage to all of the bit lines.

17. The method of claim 16, wherein the positive voltage applied to the one control gate line is greater than the positive voltage applied to the others of the source lines.

18. The method of claim 16, wherein the positive voltage applied to the one control gate line is at least double than that of the positive voltage applied to the others of the source lines.

19. A method of erasing a selected memory cell of a memory device, wherein the memory device comprises: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein one of the plurality of memory cells is a selected memory cell; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, a control gate disposed over and insulated from the floating gate, a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and an erase gate disposed over and insulated from the source region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells; the method comprising: applying a ground voltage to one of the control gate lines that is electrically connected to the control gate of the selected memory cell, and a positive voltage to all the others of the control gate lines; applying a ground voltage to all of the source lines; applying a ground voltage to all of the bit lines; applying a ground voltage to all of the select gate lines; and applying a positive voltage to one of the erase gate lines that is electrically connected to the erase gate of the selected memory cell, and a ground voltage to all the others of the erase gate lines.

20. The method of claim 19, wherein the positive voltage applied to the one of the erase gate lines is greater than the positive voltage applied to the others of the control gate lines.

21. The method of claim 19, wherein the positive voltage applied to the one of the erase gate lines is at least double than that of the positive voltage applied to the others of the control gate lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a side cross sectional view of a conventional 2-gate non-volatile memory cell.

[0020] FIG. 2 is a schematic drawing of a conventional architecture of the 2-gate non-volatile memory cell of FIG. 1.

[0021] FIG. 3 is a side cross sectional view of a conventional pair of 2-gate non-volatile memory cells.

[0022] FIG. 4 is a schematic drawing of a conventional architecture of the 2-gate non-volatile memory cells of FIG. 3.

[0023] FIG. 5 is a side cross sectional view of a conventional 4-gate non-volatile memory cell.

[0024] FIG. 6 is a schematic drawing of a conventional architecture of the 4-gate non-volatile memory cell of FIG. 5.

[0025] FIG. 7 is a schematic drawing of the 2-gate non-volatile memory cell architecture of the present invention.

[0026] FIG. 8 is a schematic drawing of an alternate embodiment of the 2-gate non-volatile memory cell architecture of the present invention.

[0027] FIG. 9 is a schematic drawing of the 4-gate non-volatile memory cell architecture of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] The present invention involves new architecture configurations for arrays of split-gate non-volatile memory cells that provide unique (random order) programming, reading and erasing of single memory cells (i.e., true single bit operation).

[0029] For the two-gate cell of FIGS. 1 and 3, the memory cell array architecture that provides true single bit operation is shown in FIG. 7. The main difference between the 2-gate single bit operation architecture of FIG. 7, and the conventional 2-gate architecture discussed above with respect to FIGS. 2 and 4, is that the horizontal control gate lines 22a (one for each row of memory cells) have been replaced with vertical control gate lines 22b and 22c (i.e., two control gate lines for each column of memory cells). Specifically, each column of memory cells includes two control gate lines: a first control gate line 22b electrically connecting together all the control gates 22 of the odd row memory cells (i.e., those memory cells in odd rows 1, 3, 5, etc.), and a second control gate line 22c electrically connecting together all the control gates 22 of the even row memory cells (i.e., those memory cells in even rows 2, 4, 6, etc.). By reorienting the control gate lines in this manner, any memory cell in the array can be individually programmed, erased and read without adversely affecting the memory state of adjacent memory cells. Exemplary (non-limiting) operational voltages to erase, program or read any given target memory cell are shown in Table 2 below:

TABLE-US-00002 TABLE 2 CG 22 Drain 16 Source 14 sel unsel sel unsel sel unsel Erase VGerase gnd gnd gnd gnd VSerinhibit Program VGprg gnd Iprog VDprginh VSprg gnd Read VGrd gnd VDrd gnd VSrd float/gnd (sel = line that intersects target memory cell) (unsel = line that does not intersect target memory cell).
Numerical (non-limiting) examples are shown in Table 3 below:

TABLE-US-00003 TABLE 3 VGerase 5-9 v VSerinhibit 3-4 v VGprg 1.2-1.7 v VDprginh 1.5-2.5 v Iprog 2-5 ua VSprg 4-8 V VGrd 0.4-2.5 V VDrd 1-2 V VSrd 0-0.6 V

[0030] During erase, only the selected cell will have a high voltage on its control gate 22 in combination with its source region 14 being at ground, so that electrons will tunnel off the floating gate 20. Any unselected cells in the same column that have a high voltage applied to their control gates 22 will also have an inhibit voltage applied to their source regions 14 that is sufficiently high to inhibit any tunneling of electrons off of the floating gate (i.e. the electrons will see positive voltages in two opposing directions).

[0031] FIG. 8 illustrates an alternate embodiment of the 2-gate single bit operation architecture. The main difference between the 2-gate single bit operation architecture of FIG. 8, and the conventional 2-gate architecture discussed above with respect to FIGS. 2 and 4, is that the horizontal source lines 14a (one for each row) have been replaced with vertical source lines 14b (one for each column). Specifically, each column of memory cells includes a source line 14b electrically connecting together all the source regions 14 for all the memory cells 10 in that column. By reorienting the source lines in this manner, any memory cell in the array can be individually programmed, erased and read without adversely affecting the memory state of adjacent memory cells. The Table 2 operational values equally apply to this embodiment.

[0032] FIG. 9 illustrates a 4-gate single bit operation architecture for the memory cell of FIG. 6. The main difference between the 4-gate single bit operation architecture of FIG. 9, and the conventional 4-gate architecture discussed above with respect to FIG. 6, is that the horizontal erase gate lines 30a (one for each pair of memory cell pairs) have been replaced with vertical erase gate lines 30b. Specifically, each column of memory cells includes an erase gate line 30b that electrically connects together all the erase gates 30 for the column of memory cells. By reorienting the erase gate lines in this manner, any memory cell in the array can be individually programmed, erased and read. Exemplary operational voltages to erase, program or read any given target memory cell are shown in Table 3 below:

TABLE-US-00004 TABLE 4 EG WL CG BL S sel unsel sel unsel sel unsel sel unsel sel unsel Erase VEGerase gnd gnd gnd gnd VCGerinhibit gnd gnd gnd gnd Program VEGprg/ gnd VWLprg gnd VCGprg gnd Iprog VBLprginh VSprg Float/ gnd gnd/0.5 v Read gnd gnd VWLrd gnd VCGrd gnd VBLrd gnd VSrd float/gnd (sel = line that intersects target memory cell) (unsel = line that does not intersect target memory cell).
Numerical (non-limiting) examples are shown in Table 4 below:

TABLE-US-00005 TABLE 4 VEGerase 8-11.5 v VCGerinhibit 3.5-8 v VEGprg 4-6 v VWLprg 0.8-1.2 v VCGprg 6-10 v VBLprginh 1-2.5 v Iprog 0.2-1 ua VSprg 3-5 V VWLrd 0.4-2.0 V VCGrd 1-2.5 V VBLrd 0.8-2 V VSrd 0-0.6 V

[0033] It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

[0034] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.