Integrated semiconductor device

Abstract

A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Claims

1. An integrated semiconductor device comprising: a silicon on insulator (SOI) substrate comprising a first silicon body, an insulation body formed on said first silicon body, and a second silicon body formed on said insulation body; a III-nitride heterostructure formed over a top surface of said SOI substrate, said heterostructure comprising a III-nitride buffer layer formed over said SOI substrate, a first III-nitride layer formed over said buffer layer, and a second III-nitride layer formed over said first III-nitride layer; a power transistor formed in said heterostructure; a driver circuit configured to drive said power transistor, said driver circuit comprising a silicon device formed in said second silicon body below said top surface; and a via extending through said heterostructure, through said second silicon body, and through said insulation body to make electrical contact between an electrode of said power transistor and said first silicon body, said via having walls lined by an insulation body and comprising conductive filler; wherein said power transistor includes a two-dimensional electron gas (2-DEG).

2. The integrated semiconductor device of claim 1, wherein said silicon device is an integrated circuit.

3. The integrated semiconductor device of claim 1, wherein said driver circuit comprises another silicon device formed in said second silicon body.

4. The integrated semiconductor device of claim 1, wherein said silicon device is positioned lateral to said transistor.

5. An integrated semiconductor device comprising: a silicon on insulator (SOI) substrate comprising a first silicon body, an insulation body formed on said first silicon body, and a second silicon body formed on said insulation body; a III-nitride heterostructure formed over a top surface of said SOI substrate, said heterostructure comprising a III-nitride buffer layer formed over said SOI substrate, a first III-nitride layer formed over said buffer layer, and a second III-nitride layer formed over said first III-nitride layer; a III-nitride power transistor formed in said heterostructure; a logic device formed in said second silicon body below said top surface, said logic device operatively coupled to a gate electrode of said III-nitride power transistor; a via extending through said heterostructure, through said second silicon body, and through said insulation body to make electrical contact between an electrode of said III-nitride power transistor and said first silicon body, said via having walls lined by an insulation body and comprising conductive filler; wherein said III-nitride power transistor includes a two-dimensional electron gas (2-DEG).

6. The integrated semiconductor device of claim 5, wherein said III-nitride power transistor is a high electron mobility transistor.

7. The integrated semiconductor device of claim 5, wherein said logic device is an integrated circuit logic device.

8. The integrated semiconductor device of claim 5, wherein said logic device is configured to supply drive signals to said gate electrode of said III-nitride power transistor.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 illustrates a cross-sectional view of a first embodiment of the present invention.

(2) FIG. 2 illustrates a cross-sectional view of a semiconductor wafer for the fabrication of a device according to other embodiments of the present invention.

(3) FIG. 3 illustrates a cross-sectional view of another III-nitride device according to the second embodiment of the present invention.

(4) FIG. 4 illustrates a cross-sectional view of a third embodiment of a device according to the present invention.

(5) FIG. 5 illustrates a cross-sectional view of a fourth embodiment of a device according to the present invention.

DETAILED DESCRIPTION OF THE FIGURES

(6) An integrated device according to the present invention includes a silicon body in which one or more IC logic devices are formed and a III-nitride power semiconductor device formed over a surface of the silicon substrate and preferably operatively coupled to at least one of the IC logic devices.

(7) Referring to FIG. 1, an integrated semiconductor device according to a first embodiment of the present invention includes an IC semiconductor logic device 32 formed in a silicon body 16, and a III-nitride power semiconductor device 12 formed over a major surface of silicon body 16. Note that IC device 32 is preferably positioned laterally to the III-nitride power device 12. In the preferred embodiment, III-nitride semiconductor device 12 may be a heterojunction power device having a schottky or an insulated gate such as a HEMT (high electron mobility transistor) examples of which are disclosed in U.S. Patent Application Publication No. 2006/0060871 and U.S. Pat. No. 5,192,987 or a III-nitride FET. IC semiconductor logic device 32 may be a silicon based driver or the like integrated circuit for driving III-nitride device 12.

(8) According to an aspect of the present invention, an insulation body 40 (e.g., an oxide body such as SiO.sub.2) is formed over IC semiconductor logic device 32 as well as III-nitride device 12. One or more vias 42 are opened in insulation body 40, each via 42 including a conductive (e.g. metal) filler 44 leading from an electrode of IC semiconductor logic device 32 to at least one electrode of III-nitride device 12. Thus, for example, a via 42 may lead from the gate electrode of III-nitride device 12 to an electrode of IC device 32 that supplies drive signals to the gate electrode.

(9) To fabricate a device according to the present invention, first a semiconductor body 16 is prepared to serve as a substrate for III-nitride device 12. Thereafter, a III-nitride body 20 (e.g. AlN) is formed over silicon body 16 using any desired technique. III-nitride body 20 may serve as a buffer layer or a transition layer.

(10) Next, IC semiconductor logic device 32 is formed in silicon body 16 on a different plane lateral to III-nitride body 20, and then the rest of III-nitride device 12 is formed on III-nitride body 20 on silicon body 16. Thus, for example, a III-nitride heterojunction device such as a high electron mobility transistor may be formed by growing an active body 21 that includes an active III-nitride heterojunction over buffer layer 20. Alternatively, a III-nitride FET may be formed over III-nitride body 20.

(11) Thereafter, insulation body 40 is formed and then planarized using, for example, CMP. Vias 42 are next opened in body 40 using any desired method and filled with conductors 44 to connect IC 32 and III-nitride device 12 to complete a device according to the present invention. Vias 42 may be 1-5 μm wide.

(12) Note that the present invention is not limited to one III-nitride body 20, but multiple III-nitride bodies 20 each for at least one III-nitride device 12 can be provided without departing from the scope and spirit of the present invention.

(13) Referring to FIG. 2, a semiconductor wafer used for fabrication of a device according to the second embodiment of the present invention includes a support substrate 10 and a III-nitride semiconductor body 12 formed over support substrate 10.

(14) According to an aspect of the present invention, support substrate 10 includes a first silicon body 14, a second silicon body 15 and an insulation body 18 interposed between first silicon body 14 and second silicon body 18. In one embodiment, first silicon body 14 may be a <111> single crystal silicon, second silicon body may be <111> single crystal silicon, and insulation body 18 may be silicon dioxide. In another embodiment, first silicon body 14 may be <100> silicon, second silicon body 15 may be <111> silicon, and insulation body 18 may be silicon dioxide.

(15) In both embodiments, an SOI (silicon on insulator) substrate is suitable. Such substrates include two silicon substrates bonded to one another by a silicon dioxide layer. The first embodiment can also be realized by a SiMox process whereby implantation of oxygen into a <111> silicon substrate followed by an annealing step forms an insulation body 18 made of silicon dioxide between a first <111> silicon body 14 and a second <111> silicon body 15. Note that second silicon) body 15 may optionally include an epitaxially grown layer thereon. Furthermore, note that other than SiMox, or silicon bonded to silicon, other methods can be used to realize a device according to the present invention.

(16) III-nitride semiconductor device 12 includes, in one preferred embodiment, a III-nitride buffer layer 20 (e.g. AlN), over second silicon body 15, and a III-nitride heterojunction formed over III-nitride buffer layer 20, that includes a first III-nitride layer 22 having one band gap (e.g. GaN) and a second III-nitride layer 24 having another band gap (e.g. AlGaN, InAlGaN, InGaN, etc.) formed over first layer 22. The composition and/or the thickness of first and second III-nitride layers 22 and 24 are selected to result in the formation of a carrier rich region referred to as a two-dimensional electron gas (2-DEG) near the heterojunction thereof.

(17) According to one aspect of the present invention, the III-nitride heterojunction can be used as the current carrying region of a III-nitride power semiconductor device (e.g. a high electron mobility transistor).

(18) Referring to FIG. 3, a III-nitride high electron mobility transistor may include first and second power electrodes 26, 28 (e.g. source and drain electrodes) coupled to the 2-DEG through second III-nitride layer 24 and gate arrangements 30 each disposed between a respective first power electrode 26 and second power electrode 28. A gate arrangement may include an insulated gate electrode or a gate electrode that makes Schottky contact to second III-nitride layer 24.

(19) In a device according to the first embodiment, active body 21 residing on buffer layer 20 may include a III-nitride heterojunction formed over III-nitride buffer layer 20, that includes a first III-nitride layer 22 having one band gap (e.g. GaN) and a second III-nitride layer 24 having another band gap (e.g. AlGaN, InAlGaN, InGaN, etc.) formed over first layer 22. The composition and/or the thickness of first and second III-nitride layers 22 and 24 are selected to result in the formation of a carrier rich region referred to as a two-dimensional electron gas (2-DEG) near the heterojunction thereof. Furthermore, body 21 may include first and second power electrodes 26, 28 (e.g. source and drain electrodes) coupled to the 2-DEG through second III-nitride layer 24 and gate arrangements 30 each disposed between a respective first power electrode 26 and second power electrode 28. A gate arrangement may include an insulated gate electrode or a gate electrode that makes Schottky contact to second III-nitride layer 24. Thus, a III-nitride device 12 in the first embodiment may include features similar to those in the second embodiment.

(20) In a device according to the second embodiment, semiconductor devices 32 may be formed in second silicon body 15. In one preferred embodiment, semiconductor devices 32 may be logic devices formed using CMOS technology for the purpose of operating the III-nitride device 12. For example, semiconductor devices 32 may be part of a driver circuit for driving III-nitride device 12. Note that in the second embodiment semiconductor devices 32 are disposed directly below III-nitride power device 12.

(21) Referring now to FIG. 4, according to the third embodiment, a via 34 that extends from the top of second III-nitride layer 24 to, for example, first silicon body 14 may be provided to allow for electrical communication between one of the power electrodes 28 (e.g. source or drain) and first silicon body 14. Via 34 may include an insulation body 36 on the walls thereof, and an electrically conductive body 38 (e.g. a metallic body or conductive semiconductor body such as polysilicon) connecting electrode 28 to first silicon body 14.

(22) Referring now to FIG. 5, in which like numerals identify like feature, in a device according to the fourth embodiment of the present invention, a portion of the III-nitride body 12 is removed to expose an area of second silicon body 15. Semiconductor devices 32 are formed in the exposed area of second silicon body 15 lateral to the III-nitride power device 12, rather than being disposed directly below the III-nitride power semiconductor device 12.

(23) A wafer used in a device according to the present invention can be used to devise power devices for high voltage applications because of the presence of insulation body 18, which reduces leakage current into the substrate and improves the breakdown voltage of the device. For example, when insulation body 18 is silicon dioxide, its thickness can be 0.1 to 2 microns to increase the breakdown voltage of the device. In one embodiment, for instance, silicon body 18 may be about 0.5 microns thick for a 700-1000 volt III-nitride power device.

(24) Note further that silicon body 14 and/or silicon body 15 may be doped with N-type dopants or P-type dopants. Thus, silicon bodies 14, 16 may be N++ doped or P++ doped. N++ doped or P++ doped first silicon body can improve the breakdown capability of the device by taking advantage of the resurf effect.

(25) Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.