Fin field effect transistor (FinFET)

Abstract

A FinFET whose fin has an upper portion doped with a first conductivity type and a lower portion doped with a second conductivity type, and the junction between the upper portion and the lower portion acts as a diode. The FinFET further includes: at least one layer of high-k dielectric material (for example Si.sub.3N.sub.4) adjacent at least one side of the fin for redistributing a potential drop more evenly over the diode. Examples of the k value for the high-k dielectric material are k≧5, k≧7.5, and k≧20.

Claims

1. A fin field effect transistor (FinFET) comprising: a fin having an upper portion and a lower portion extending above a substrate, the upper portion being doped with a dopant of a first conductivity type, the lower portion being doped with a dopant of a second conductivity type different from the first conductivity type, wherein a junction between the upper portion and the lower portion acts as a diode; at least one layer of high-k dielectric material adjacent to at least one side of the fin, wherein the high-k dielectric material extends in a first plane parallel to the fin and does not extend in a second plane in perpendicular to the fin, wherein the second plane is at a bottom plane of the fin; and a shallow trench isolation layer provided above the substrate and adjacent to the layer of high-k dielectric material, wherein the junction is between a top surface of the shallow trench isolation layer and a bottom surface of the shallow trench isolation layer.

2. The FinFET according to claim 1, wherein the at least one layer of high-k dielectric material has a k value of k≧5.

3. The FinFET according to claim 1, wherein the at least one layer of high-k dielectric material has a k value of k≧20.

4. The FinFET according to claim 3, wherein the at least one layer of high-k dielectric material is HfO.sub.2.

5. The FinFET according to claim 1, wherein a top surface of the high-k dielectric material is level with a top surface of the shallow trench isolation layer.

6. The FinFET according to claim 1, wherein the high-k dielectric material does not extend to a top surface of the substrate.

7. The FinFET according to claim 1, wherein the high-k dielectric material surrounds a portion of the lower portion of the fin.

8. The FinFET according to claim 1, wherein the high-k dielectric material surrounds the junction between the upper portion and the lower portion.

9. The FinFET according to claim 1, wherein the fin further comprises a source and a drain separated by a channel region, the channel region of the fin being surrounded by a gate region on three sides.

10. The FinFET according to claim 1, wherein the layer of high-k dielectric material extends from a position which is above a bottom surface of the shallow trench isolation layer upwardly to a position which is level with a top surface of the shallow trench isolation layer.

11. The FinFET according to claim 1, wherein a portion of the high-k dielectric material covers the junction and the portion of the high-k dielectric material is embedded in the shallow trench isolation layer.

12. A fin field effect transistor (FinFET) comprising: a fin having an upper portion and a lower portion extending above a substrate, the upper portion being doped with a dopant of a first conductivity type, the lower portion being doped with a dopant of a second conductivity type different from the first conductivity type, and a junction between the upper portion and the lower portion acts as a diode; at least one layer of high-k dielectric material adjacent to at least one side of the fin, wherein the high-k dielectric material extends in a first plane parallel to the fin and does not extend in a second plane in perpendicular to the fin, wherein the second plane is at a bottom plane of the fin; a shallow trench isolation layer provided above the substrate and adjacent to the layer of high-k dielectric material, wherein a portion of the high-k dielectric material covers the junction and the portion of the high-k dielectric material is embedded in the shallow trench isolation layer; a gate region formed on top of and around the sides of the fin; a channel region formed below the gate region; and a punch through stopper layer provided in the lower portion of the fin below the channel region.

13. The FinFET according to claim 12, wherein the at least one layer of high-k dielectric material has a k value of k≧5.

14. The FinFET according to claim 12, wherein a top surface of the layer of high-k dielectric material is lower than a top surface of the fin and higher than the junction.

15. The FinFET according to claim 12, wherein the high-k dielectric material is embedded in the shallow trench isolation layer and the junction is between a top surface of the shallow trench isolation layer and a bottom surface of the shallow trench isolation layer.

16. A method of fabricating a fin field effect transistor (FinFET), the method comprising the steps of: etching (s4) the substrate to provide a fin extending above a substrate, wherein the fin has an upper portion and a lower portion, the upper portion being doped with a dopant of a first conductivity type, the lower portion being doped with a dopant of a second conductivity type different from the first conductivity type, wherein a junction between the upper portion and the lower portion acts as a diode; depositing (s6) a layer of high-k dielectric material adjacent to at least one side of the fin, wherein the high-k dielectric material extends in a first plane parallel to the fin and does not extends in a second plane in perpendicular to the fin, wherein the second plane is at a bottom plane of the fin; depositing (s8) a shallow trench isolation layer above the substrate and adjacent to the layer of high-k dielectric material, wherein the junction is between a top surface of the shallow trench isolation layer and a bottom surface of the shallow trench isolation layer; providing (s10) a gate region on top of and around the sides of the fin; and implanting dopants (s12) in the fin to form the active semiconductor areas.

17. The method of fabricating the FinFET according to claim 16, wherein the step of depositing (s6) a layer of high-k material comprises depositing (s6) at least one layer of high-k dielectric material adjacent at least one side of the fin for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion is connected to a first potential and the lower portion is connected to a second potential thereby providing the potential drop across the junction.

18. The method of fabricating the FinFET according to claim 16, wherein the step of depositing (s6) a layer of high-k dielectric material comprises depositing a layer of high-k dielectric material with a k value of k≧5.

19. The method of fabricating the FinFET according to claim 16, wherein the step of depositing (s6) a layer of high-k dielectric material comprises depositing a layer of high-k dielectric material with a k value of k≧7.5.

20. The method of fabricating the FinFET according to claim 16, wherein the step of depositing (s6) a layer of high-k dielectric material adjacent at least one side of the fin comprises depositing (s6) a layer of high-k dielectric material adjacent opposite sides of the fin.

Description

(1) Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic view (not to scale) of a first embodiment of a bulk FinFET;

(3) FIG. 2 is a schematic illustration (not to scale) of a cross-section taken through the fin outside the gate of the bulk NMOS FinFET of FIG. 1;

(4) FIG. 3 is a schematic illustration of a method of fabrication of the FinFET illustrated in FIGS. 1 and 2;

(5) FIG. 4 is a schematic illustration (not to scale) of a cross-section taken through the fin outside the gate of a second embodiment of a FinFET;

(6) FIG. 5 is a schematic diagram of the simulated reverse bias diode characteristics for various FinFETs;

(7) FIG. 6 is a schematic diagram demonstrating the RESURF effect around n/p diode junction for two FinFETs;

(8) FIG. 7 is a schematic illustration of a 2-input NAND logic gate in CMOS technology which is illustrative of the possible advantages of the leakage reduction demonstrated in FIG. 5 on standard cell level; and

(9) FIG. 8 is a full three-dimensional simulation of the total leakage current of the top NMOS transistor in FIG. 7, where a fin width of 15 nm, a typical value for the 22 nm node has been chosen.

(10) FIG. 1 is a schematic view (not to scale) of a first embodiment of a bulk FinFET 100. The FinFET 100 comprises a substrate 20 of silicon. The FinFET 100 includes a narrow rectangular fin 12. Fins are typically between 10 nm and 30 nm wide. In this embodiment the fin 12 is approximately 20 nm wide. The fin 12 protrudes from the substrate 20 in a direction perpendicular to the plane of the substrate 20. The active top part of the fin 12 is 50 nm high (typically for fins this is 40-60 nm). The bottom part of the fin 12 is approximately 200 nm high. The fin 12 includes a source region 14 and a drain region 16. The source and drain regions 14, 16 of the fin 12 are separated by a layer 18 of SiO.sub.2, known as the shallow trench isolation or the STI 18. In this embodiment the STI 18 has a thickness of approximately 250 nm. Between the STI 18 and the fin there is a 10 nm wide layer 26 of HfO.sub.2 (a high-k dielectric material) which extends along the length of the lower portion of the fin 12. The HfO.sub.2 has a typical k value of k=21. The high-k dielectric layer 26 also extends between the substrate 20 and the STI 18. The high-k dielectric layer 26, which is not present in known FinFETs, will be described in more detail with reference to FIG. 2.

(11) A gate region 22 is located between the source region 14 and the drain region 16. The gate region 22 is located on top of the STI 18. The gate region 22 extends over and across the fin 12. The fin 12 also comprises a channel region 24 located between the source region 14 and the drain region 16 and under the gate region 22. As is shown in FIG. 1 the gate region 22 wraps around the fin 12 from three sides. As a result the gate 22 has excellent electrostatic control over the channel region 24 of the fin 12.

(12) The FinFET 100 illustrated in FIGS. 1 and 2 is an NMOS FET. The source region 14 and the drain region 16 of the fin 12 are heavily doped with n-type semiconductor dopants. The channel region 24 is located between the source 14 and the drain 16 regions of the fin 12 in the upper portion of the fin 12. The channel region 24 can be undoped or lightly doped.

(13) As explained above, a problem with known bulk FinFETs is that at high bias voltages FinFETs suffer from punch-through leakage. In known bulk FinFETs, a leakage path exists from the source region to the drain region through the part of the fin which is not controlled by the gate, i.e. the portion of the fin adjacent to the STI and below the channel region.

(14) FIG. 2 is a schematic illustration (not to scale) of a cross-section taken through the fin outside the gate i.e. through the source 14 or drain 16 of the bulk NMOS FinFET 100 of FIG. 1.

(15) In order to eliminate the leakage current occurring in known bulk FinFETs caused by punch through between the source and the drain regions, the fin 12 of the FinFET 100 is subdivided into two portions 30, 32.

(16) The upper portion 30 of the source and the drain regions 14, 16 is highly doped by an ion implantation process with n-type dopant. A p-type punch-through stopper (PTS) dopant is implanted in the lower portion 32 of the fin 12 directly below the channel region 24.

(17) The subdivision of the fin 12 into oppositely doped upper and lower portions 30, 32, however, causes an abrupt n/p junction 34 to be formed between each of the source 14 and drain regions 16 and the lower portion 32 of the fin. As is shown schematically in FIG. 2, the abrupt n/p junction 34 is located slightly below the surface level of the STI 18.

(18) The purpose of oppositely doping the upper and lower portions 30, 32 of the fin 12 is that the junction 34 between the differently doped portions of the fin 12 inhibits leakage current between the source 14 and drain 16.

(19) A disadvantageous effect of the highly abrupt n/p junction 34, however, is that the junction 34 acts as a diode, as shown schematically in FIG. 2.

(20) As explained above, the abruptness of the junctions formed between the source and drain regions 14, 16 and the lower portion 32 of the fin 12 leads to leakage currents formed by band-to-band tunneling (BTBT). Although BTBT could be reduced by lowering the doping levels in the source and drain regions 14, 16, this step would also lead to series resistance between source/drain and channel, while reducing the punch-through stopper dose would reduce the efficacy of the punch through stopper (PTS) layer protection described above.

(21) In standby, the largest potential drop over the reverse-biased source/substrate and drain/substrate diodes equals the supply voltage V.sub.dd. However, band-to-band tunneling is driven essentially by the electric field, which is the spatial gradient of the potential. That means that if the potential drop can be redistributed more evenly over the diode the band-to-band tunneling can be reduced.

(22) In the embodiment of FIGS. 1 and 2, redistributing the potential drop is implemented by placing a layer 26 of HfO.sub.2 (a high-k dielectric) adjacent to the n/p diode 34.

(23) As can be see in FIGS. 1 and 2, the layer 26 of high-k dielectric is adjacent to and extends along the lower portion 32 of the fin 12. The high-k dielectric layer 26 extends in a plane parallel to the fin 12. The high-k dielectric layer 26 surrounds the junction 34 between the upper portion 30 and the lower portion 32 of the fin 12. The high-k dielectric layer 26 also lies beneath the SiO.sub.2 of the STI trench 18 surrounding the lower portion 32 of the fin 12. The high-k dielectric layer 26 also extends in a plane parallel to the plane of the substrate 20. The high-k dielectric layer 26 forms a liner between the STI 18, the fin 12 and the substrate 20.

(24) A high-k dielectric is an insulating material with a high dielectric constant in comparison to SiO.sub.2 (k=3.9). Examples are silicon nitride (k=7.5) or HfO.sub.2 (k>20). The effect of its high dielectric permeability is to force the electric field to penetrate through the high-k dielectric layer 26. As is explained in more detail later with reference to FIG. 6, the high-k dielectric layer 26 reduces the local electric field strength near the junction 34. This effect is known as the RESURF effect (reduced surface field). The RESURF effect lowers the local electric field strength across the junction 34, thereby reducing the effects of BTBT without requiring a reduction in doping levels.

(25) FIG. 3 is a schematic illustration of a method of fabrication of the FinFET illustrated in FIGS. 1 and 2.

(26) In step s2, the substrate 20 is provided. The substrate is a bulk Si wafer.

(27) In step s4, the substrate 20 is etched to provide the fin portion 12 of the FinFET 100. The fin 12 is a rectangular shaped protrusion of semiconductor material extending perpendicularly to the plane of the substrate 20.

(28) In step s6, the high-k dielectric layer 26 is deposited on top of the substrate 20 and on both sides of the fin 12 along the length of the fin 12 so that the high-k dielectric layer 26 is provided directly adjacent the fin 12 on opposite sides of the upper portion 30 of the fin 12. The high-k dielectric layer 26 is 10 nm thick. Particularly effective thicknesses for the high-k layer are thicknesses falling in the range of 5-10 nm on either side of the junction.

(29) In step s8, the SiO.sub.2 shallow trench isolation (STI) layer 18 is provided. The STI 18 is formed on top of the high-k layer 26 by depositing SiO.sub.2 on areas either side of the fin 12 in a similar fabrication method as is used in conventional planar bulk CMOS fabrication. Once the STI 18 has been deposited on top of the high-k layer 26, it is planarised. Unlike in the planar bulk CMOS fabrication process, however, in this FinFET fabrication process, the STI is then etched back after planarisation so that the side walls of the fin 12 are exposed. The high-k dielectric layer 26 HfO.sub.2 acts as a liner positioned between the STI 18 and the opposite sides of the upper portion 30 of the fin 12.

(30) In step s10, the gate 22 is provided. Layers of dielectric, metal and polysilicon material are deposited on top of the STI 18 and across the top of and around the sides of the fin 12 and etched to form the gate 22 illustrated in FIG. 1.

(31) In step s12, after gate etch, dopants are implanted in the fin 12 to form the active semiconductor areas. The source and drain regions 14, 16 are heavily doped by an ion implantation process using n-type dopants for NMOS and p-type for PMOS.

(32) For the sake of simplicity, the step s12 of doping by ion implantation is explained as occurring after the step s10 of gate etch, since this is when the final heavy doping of the source and drain regions 14, 16 of the exposed upper portion 30 of the fin 12 typically takes place. As will now be explained, however, doping the different types of layers and regions may take place at various stages during fabrication.

(33) For example, the source and drain are implanted after the gate has been formed, the gate acting as a mask for the channel region which should not receive the source/drain implant. The PTS is implanted before gate formation. The source/drain are implanted more shallowly, but with higher concentration.

(34) The channel can be implanted before or after gate etch; in the latter case the channel will not be homogeneously doped (this is known as pockets or halos).

(35) Typically the PTS profile starts directly below the active (top part) of the fin and extends between 40 and 100 nm downwards.

(36) Various other implementation details are possible, as follows. A WELL may be used. The well is meant to isolate transistors from each other and to isolate the source/drain from the substrate. An NMOS is made in a P-WELL, a PMOS is made in an N-WELL. A VT-Adjust (VTA) may be used, and is intended to tune the threshold voltage. The PTS is intended to prevent deep leakage between the source and the drain. The HALO (=POCKET) is intended to make the VT less dependent on the gate length.

(37) There are many different scenarios in which implantations are done at different steps in the process. The halo is always implanted after the gate is formed, the other three implementations discussed directly above are typically (but not necessarily) prior to that.

(38) In a bulk FinFET normally only the WELL and the PTS are implanted, prior to gate deposition. The WELL has a low concentration (typically <1e17/cm.sup.3) which is not enough to stop punch-through, the PTS has concentrations around 1e18/cm.sup.3.

(39) Various options are possible with regard to the timing and the implementation of the earlier mentioned planarising actions, including the following three possibilities:

(40) (i) the high-k layer is deposited to the level of the top of the fin and then subject to planarisation before the STI layer is applied;

(41) (ii) the STI layer and the high-k layer are etched back simultaneously to expose the upper portion of the fin; and

(42) (iii) the high-k layer is deposited only to the level that the STI layer will be at after etching, the STI then being deposited over the high-k layer, planarised and then etched back to the same height as the high-k layer.

(43) Of the above, option (ii) is the easiest from a manufacturing point of view.

(44) Returning to consideration of the total process, one particularly suitable example of the order of various doping and etching steps is the following sequence: WELL Fin etch high-k and STI fill and etch back PTS Gate source/drain.

(45) FIG. 4 is a schematic illustration (not to scale) of a cross-section taken through the fin outside the gate i.e. through the source 14 or drain 16 of a second embodiment of a FinFET 200. Where features are the same as for the FinFET 100 of FIGS. 1 and 2, the same reference numerals have been used.

(46) The fin 12 of the FinFET 200 of this embodiment is subdivided into an upper portion 30 and a lower portion 32. The upper portion 30 of the fin 12 forms the source and the drain regions 14, 16. The source and the drain regions 14, 16 are highly doped with n-type dopant (NMOS). The lower portion 32 of the fin is doped with a p-type punch-through stopper dopant implanted in the lower portion 32 of the fin 12 directly below the channel 24.

(47) To prevent the abruptness of the junctions formed between the source and drain regions and the lower portion of the fin from leading to leakage currents formed by band-to-band tunneling (BTBT), a layer 28 of HfO.sub.2 (i.e. a high-k dielectric layer) is placed adjacent to the n/p junction 34.

(48) As can be see in FIG. 4, the high-k dielectric layer 28 of is adjacent to and extends along the lower portion 32 of the fin 12. The high-k dielectric layer 28 extends in a plane parallel to the fin 12. The high-k dielectric layer 28 surrounds the junction 34 between the upper portion 30 and the lower portion 32 of the fin 12.

(49) In contrast to the first embodiment, in this embodiment, the high-k dielectric layer 28 does not lie beneath the SiO.sub.2 of the STI trench 18 surrounding the lower portion 32 of the fin 12. The high-k dielectric layer 28 does not extend in a plane parallel to the plane of the substrate 20. The high-k dielectric layer 28 does not extend to the top surface of the substrate 20. Thus in this embodiment, the high-k dielectric layer 28 surrounds the lower portion 32 of the fin 12 in the region of the n/p junction 34 only.

(50) FIG. 5 is a schematic diagram of the simulated reverse bias diode characteristics for various FinFETs. The vertical axis 40 shows the leakage current I.sub.leak in arbitrary units.

(51) The horizontal axis 42 shows the supply voltage V.sub.dd, in Volts. Curve 46 shows the simulated diode characteristic for FinFET 200 shown in cross-section in FIG. 4, in which the high-k dielectric layer is Si.sub.3N.sub.4 (k=7.5). Curve 48 shows the simulated diode characteristic for a FinFET constructed in the same way as the FinFET 200 shown in cross-section in FIG. 4, but in which the dielectric is a material with a very high-k value (k=20). Curve 44 shows the simulated diode characteristic for a reference FinFET without a high-k dielectric layer.

(52) Clearly, for supply voltages around 1V, for the 22 nm node, diode leakage can be reduced by approximately 1.5 orders of magnitude, i.e. by approximately a factor of 30, thanks to the RESURF effect caused by the high-k layer.

(53) FIG. 6 is a schematic diagram demonstrating the RESURF effect around n/p diode junction for two FinFETs. For each FinFET only half of the symmetric structure is shown. The junction position is indicated by the diode symbol. The vertical axis 52 shows the vertical height Y of the FinFET in micrometers (μm). The horizontal axis 54 shows the horizontal distance X from the central axis of the fin 12 in micrometers (μm).

(54) The left hand side of the diagram 50 depicts a standard FinFET with SiO.sub.2 everywhere in the STI area, i.e. with no high-k dielectric layer. The right hand side of the diagram 60 shows a cross section of a FinFET with a high-k dielectric layer.

(55) In both the left and the right hand side diagrams, the central portion 56 of the FinFETs is a silicon fin. In the left hand side diagram 50, the portions 58 of the FinFET adjacent the central portion 56 are SiO.sub.2. In the right hand side diagram 60, the portion 62 of the FinFET adjacent the fin portion 56 is a 10 nm wide high-k dielectric layer or liner. The high-k insulating liner is adjacent to the p/n junction. The portion 58 of the FinFET adjacent the high-k dielectric layer 62 but further from the fin portion 56 is SiO.sub.2.

(56) The diagram shows the distribution of the iso-potential lines across each FinFET. It is clear from the diagrams that the iso-potential lines for the FinFET with high-k liner, as shown in the right hand FIG. 60, are distributed over a larger distance in the y-direction, demonstrating the RESURF effect.

(57) Simulations show that a leakage improvement of between 10× to 100× can be achieved for all combinations of fin width between 10-30 nm, punch-through stopper (PTS) concentrations between 10.sup.18 and 10.sup.19 atom/cm.sup.3 and source/drain doping levels around 10.sup.20 atom/cm.sup.3. Also the mechanism of tunneling (whether direct tunneling or trap-assisted tunneling) plays no role in the obtainable improvement.

(58) FIG. 7 is a schematic illustration of a 2-input NAND logic gate 70 in CMOS technology which is illustrative of the possible advantages of the leakage reduction demonstrated in FIG. 5 on standard cell level.

(59) In FIG. 7 two PMOS transistors 72 are connected in parallel, with their substrate contacts at the logical “1”. Two NMOS transistors 74, 76 are connected in series with their substrate contacts at the logical “0”. In the depicted state of the cell, three source/drain to substrate diodes are reverse-biased and leak to the substrate contact, as indicated by arrows 78. Thus, in the bias condition depicted in the 2-input NAND logic gate 70 shown in FIG. 7, three out of four NMOS source/drain to substrate diodes are reverse-biased and will contribute to the total leakage of the cell.

(60) Note that the situation depicted in FIG. 7 is only illustrative. For other bias conditions other diodes will leak, and for any digital cell in CMOS technology, whether SRAM or logical, there are source/drain diodes which are reverse-biased, their leaking current contributing to and possibly dominating the total standby power consumption.

(61) FIG. 8 shows a full three-dimensional simulation of the total leakage current of the top NMOS transistor 74 in FIG. 7, where a fin width of 15 nm, a typical value for the 22 nm node, has been chosen.

(62) The vertical axis 80 shows the leakage current I.sub.leak in Amps/μm.

(63) The horizontal axis 82 shows the supply voltage V.sub.dd, in Volts. Curve 86 shows the simulated diode characteristic for the top NMOS transistor 74 of FIG. 7, which has a 10 nm wide high-k dielectric layer of Si.sub.3N.sub.4 (k=7.5). Curve 88 shows the simulated diode characteristic for an NMOS transistor constructed in the same way as the top NMOS transistor 74 of FIG. 8 but with a very high-k dielectric liner (k=20). Curve 84 shows the simulated diode characteristic for the reference case of an NMOS transistor without a liner along the vertical source/drain to substrate diodes.

(64) The leakage current I.sub.leak is normalised to the effective width of the FinFET (W.sub.eff=2H.sub.fin+W.sub.fin), where W.sub.eff is the effective width of the fin, H.sub.fin is the height of the fin, and W.sub.fin is the width of the fin. The low-power leakage target is indicated for the 22 nm node.

(65) Again the graph demonstrates that the high-k liner reduces transistor leakage by about 1.5 order of magnitude, but what is even more important is that the normalized (to the total effective width of the FinFET) leakage can be reduced to below 10 pA/μm, which, as shown in FIG. 8, is the LP leakage target specification 90 for the low-standby power (LP) technology. In other words, the invention may facilitate the use of bulk FinFETs for low-power applications.

(66) Although in the above embodiments the substrate 20 has been described as silicon, the substrate 20 can be any suitable substrate material compatible with integrated circuit fabrication processes on bulk planar wafers. Similarly, although the STI 18 has been described as comprising SIO.sub.2, the STI can be any suitable isolation material compatible with integrated circuit fabrication processes on bulk planar wafers.

(67) Although the fin 12 has been described as rectangular shaped, the fin may also have other shapes. For example the fin may have slightly rounded top corners. The fin 12 can also be slightly tapered reducing in width towards the bottom. The fin 12 has been described as extending 20 nm above the STI 18 and as being 20 nm wide. The fin can be of different widths and heights as desired for the particular application. A typical range for the fin width is 10-30 nm.

(68) Although the figures show a tilted source-drain implementation in which the n/p junction 34 is located slightly below the STI 18 surface, FinFETs with n/p junctions located higher or lower in the fin 12 are also envisaged.

(69) The embodiments have been described with reference to NMOS devices. However, the invention is equally applicable to PMOS devices. Thus although the source and drain regions 14, 16 have been described as being heavily doped with n type dopants, they could also be doped with p-type dopants.

(70) Whilst the high-k layer 26, 28 has been explained as being comprised of HfO.sub.2, (for which k=21), the high-k dielectric material may be any insulator compatible with CMOS fabrication technologies with a higher dielectric constant k than that of SiO.sub.2. For example, another suitable material is Si.sub.3N.sub.4 (for which k=7.5). More generally, any material with a k value higher than that of SiO.sub.2, i.e. k=3.9, may be used. For example, a k-value of k=5 may be used, to provide redistribution of the potential drop across the diode etc., to at least some extent, even though higher values such as, for example, k=7.5 (for Si.sub.3N.sub.4) and k=21 for HfO.sub.2, will tend to provide an even larger improvement. k=21 is the k-value of bulk HfO.sub.2, although deposited layers may sometimes have values differing slightly therefrom. Generally, k-values of k≧20 are particularly advantageous. Examples of other possible materials for the high-k dielectric layer include HfSiO, ZrO.sub.2, ZrSiO, and SrTiO.sub.3.

(71) Although the high-k dielectric layers 26, 28 have been described as being located on both side faces of the fin adjacent the junctions, it is also possible to place the high-k layer only on one side of the fin.

(72) In the embodiment illustrated in FIGS. 1 and 2, the layer of high-k dielectric material lies beneath the full extent of the SiO.sub.2 of the STI trench and completely surrounds the lower portion of the fin 12. It is also envisaged, however, that the layer of high-k dielectric material could extend only partially under the SiO.sub.2 of the STI trench. Alternatively, the layer of high-k dielectric could extend only along part of the length of the fin 12 adjacent the p/n junction 34. Furthermore, it is also envisaged that the layer of high-k dielectric material could also extend above of the surface of the STI trench, partly to cover the upper portion of the fin.

(73) Whilst the high-k layer 26, 28 has been described as being 5-10 nm thick, it is also possible for the layer to be thicker or thinner according to the desired application.

(74) Although the leakage current has been described as being reduced by a factor of 30, according to the type and form of dielectric layer, the leakage current may be reduced by a factor of between 10 and 100.

(75) Whilst the above embodiments are devices with 32 nm node CMOS fabrication, and the invention is particularly suited to 32 nm and beyond technology, nevertheless the invention is also applicable to other node specifications, for example 22 nm node fabrication.

(76) In terms of fabrication, although the step of providing the fin has been described as by etching, any other suitable methods of providing the fin, such as by machining, could be used.

(77) Additionally, the step of providing the high-k dielectric layer has been described as by depositing, any suitable way of providing a layer between the fin and the STI on one or two opposite sides of the fin could be used.

(78) Similarly the STI layer and the gate may be provided by any suitable method, such as deposition or coating. The high-k dielectric layer may be planarised before the STI is planarised or at the same time. The STI may be etched back after planarisation before the high-k dielectric layer is etched back so that the side walls of the fin are exposed or at the same time.

(79) The gate may be provided by any suitable method such as deposition and etching or stacking.

(80) Whilst the step of doping has been explained as occurring after the gate stacking and etching, various doping stages may take place earlier. For example, the p-type ion implantation to form the punch through stopper (PTS) may take place before the deposition of the k-type dielectric.

(81) Other doping steps, such as forming a well of p-type silicon under the PTS layer, may also take place before the gate etch.

(82) Typical concentrations of dopants may be: source/drain 14, 16: 10.sup.20 atom/cm.sup.3; channel region 24: <10.sup.17 atom/cm.sup.3; punch-through stopper (not shown): 10.sup.18-10.sup.19 atom/cm.sup.3; well (not shown): 10.sup.16-10.sup.17 atom/cm.sup.3.

(83) Other doping concentrations may also be selected according to the desired application.

(84) It should be noted that terminology such as top, over, above, under, below vertical, horizontal are used throughout the description, for the purpose of explaining the relative positions of the features of the present invention. These terms are not intended to limit the orientation of the device.