Power semiconductor device with an auxiliary gate structure

Abstract

The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.

Claims

1. A III-nitride power semiconductor based heterojunction device comprising a low voltage terminal, a high voltage terminal and a control terminal and further comprising: an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising: a first III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas; a first terminal operatively connected to the III-nitride semiconductor region and further connected to the low voltage terminal; a second terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region and further connected to the high voltage terminal; an internal gate terminal operatively connected to an active gate region formed over the III-nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal; a voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, wherein the voltage clamp circuit comprises a first connection to the internal gate terminal of the active heterojunction transistor and a second connection to the low voltage terminal; a turn-on circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-on operation, and wherein the turn-on circuit is configured to control a transient gate current in the internal gate terminal and a transient current in the voltage clamp circuit during the turn-on operation, wherein the turn-on circuit comprises a third connection to the internal gate terminal of the active heterojunction transistor; an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, and wherein the on-state circuit is configured to control a steady-state gate current in the internal gate terminal and a steady-state current in the voltage clamp circuit during the on-state operation, wherein the on-state circuit comprises a fourth connection to the internal gate terminal of the active heterojunction transistor and a fifth connection to the control terminal; a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state, and wherein the turn-off circuit is configured to control a transient gate current from the internal gate terminal to the control terminal, and wherein the turn-off circuit is operatively connected to the internal gate terminal and the control terminal during the turn-off operation and the off-state, wherein the turn-off circuit comprises a sixth connection to the internal gate terminal of the active heterojunction transistor and a seventh connection to the control terminal; and wherein the active heterojunction transistor, the voltage clamp circuit, the turn-on circuit, the on-state circuit and the turn-off circuit are monolithically integrated.

2. The heterojunction power device according to claim 1, wherein the turn-on circuit further comprises an eighth connection to the control terminal.

3. The heterojunction power device according to claim 2, further comprising an additional external terminal configured to act as the input of the turn-on circuit.

4. The heterojunction power device according to claim 1, further comprising an additional external terminal configured to act as an input of the turn-on circuit.

5. The heterojunction power device according to claim 1, wherein the turn-on circuit further comprises a resistor.

6. The heterojunction power device according to claim 1, wherein the turn-on circuit further comprises a current source and an enhancement mode transistor.

7. The heterojunction power device according to claim 6, wherein the current source comprises a low voltage transistor, a gate terminal and a resistor, wherein a first terminal of the current source comprises a first terminal of the low voltage transistor, a second terminal of the current source is operatively connected to a gate terminal of the low voltage transistor, and the resistor is connected in series between the second terminal of the current source and a second terminal of the low voltage transistor.

8. The heterojunction power device according to claim 6, wherein the turn-on circuit further comprises a capacitor.

9. The heterojunction power device according to claim 1, wherein the on-state circuit further comprises a resistor.

10. The heterojunction power device according to claim 1, wherein the on-state circuit further comprises a current source.

11. The heterojunction power device according to claim 10, wherein the current source comprises a low voltage transistor, a gate terminal and a resistor, wherein a first terminal of the current source comprises a first terminal of the low voltage transistor, a second terminal of the current source is operatively connected to a gate terminal of the low voltage transistor, and the resistor is connected in series between the second terminal of the current source and a second terminal of the low voltage transistor.

12. The heterojunction power device according to claim 1, wherein the turn-off circuit further comprises a depletion mode low voltage transistor.

13. The heterojunction power device according to claim 12, wherein the turn-off circuit further comprises an enhancement mode low voltage transistor connected in parallel to the depletion mode low voltage transistor, wherein a gate terminal of the enhancement mode low voltage transistor is operatively connected to either the low voltage terminal or the high voltage terminal.

14. The heterojunction power device according to claim 1, wherein the turn-off circuit further comprises an enhancement mode low voltage transistor, wherein a gate terminal of the enhancement mode low voltage transistor is operatively connected to either a source terminal or a drain terminal of the enhancement mode low voltage transistor.

15. The heterojunction power device according to claim 1, wherein the turn-off circuit further comprises a depletion mode low voltage transistor, a capacitor, a resistor and an enhancement mode low voltage transistor.

16. The heterojunction power device according to claim 1, wherein the voltage clamp circuit further comprises: an enhancement mode low voltage transistor, wherein a drain terminal of the enhancement mode low voltage transistor is operatively connected to the internal gate terminal of the active heterojunction transistor, a source terminal of the enhancement mode low voltage transistor is operatively connected to the low-voltage terminal; and a potential divider, wherein a mid-point of the potential divider is operatively connected to a gate terminal of the enhancement mode low voltage transistor.

17. The heterojunction power device according to claim 16, wherein the potential divider comprises any one or more of: at least one resistive element; at least one capacitor; and at least one low voltage source-gate connected heterojunction transistor.

18. The heterojunction power device according to claim 16, wherein the voltage clamp circuit further comprises: a low voltage depletion mode transistor, wherein a drain terminal of the low voltage depletion mode transistor is operatively connected to the mid-point of the potential divider, a gate terminal of the low voltage depletion mode transistor is operatively connected to the low voltage terminal; and a resistor connected between a source terminal of the low voltage depletion mode transistor and the low voltage terminal.

19. The heterojunction power device according to claim 1, wherein the voltage clamp circuit further comprises two or more low voltage enhancement mode transistors connected in series, wherein a gate terminal of each of said low voltage enhancement mode transistors is operatively connected to a respective drain terminal of the low voltage depletion mode transistors.

20. The heterojunction power device of claim 1, further comprising one or more monolithically integrated temperature compensated circuits, wherein the one or more monolithically integrated temperature compensated circuit comprise: a low voltage heterojunction transistor; a first resistor connected in series with the low-voltage heterojunction transistor; a second resistor connected in parallel with the low-voltage heterojunction transistor; and wherein the one or more monolithically integrated temperature compensated circuit are configured to reduce an effect of variations in temperature on a circuit behaviour of connected components.

Description

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

(1) The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.

(2) FIG. 1 shows schematically the cross section in the active area of a prior art pGaN HEMT;

(3) FIG. 2 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure;

(4) FIG. 3 shows a circuit schematic representation of one embodiment of the proposed disclosure as shown in the schematic cross section of FIG. 2;

(5) FIG. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure in which a low on-state voltage diode is connected in parallel between the drain and the source of the auxiliary transistor;

(6) FIG. 4B illustrates a 3D schematic representation of the embodiment of FIG. 4A;

(7) FIG. 4C shows the cross section of the low voltage diode as used in embodiment of FIG. 4A;

(8) FIG. 5 shows a circuit schematic representation of a further embodiment of the proposed disclosure in which the drain (gate) terminal and the source terminal of the auxiliary transistor are available as external gate terminals;

(9) FIG. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a second auxiliary transistor is connected in parallel with a first auxiliary transistor where the drain (gate) terminal of the first low auxiliary transistor is connected to the source terminal of the second auxiliary transistor and the source terminal of the first auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor;

(10) FIG. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a resistor is added between the drain terminal and gate terminal of the second auxiliary transistor;

(11) FIG. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an additional resistor is added between the source terminal of the auxiliary transistor (drain terminal of the second auxiliary transistor) and source terminal of the active device;

(12) FIG. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor is added between the drain terminal and gate terminal of the second auxiliary transistor. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor;

(13) FIG. 10 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor is added between the drain terminal and gate terminal of the second auxiliary transistor. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor;

(14) FIG. 11 shows a circuit schematic representation of one embodiment of the proposed disclosure which comprises a power semiconductor heterojunction device comprising an active high voltage heterojunction transistor, a turn-on circuit, an on-state circuit, a turn-off circuit and a voltage clamp circuit.

(15) FIG. 12A shows a circuit schematic representation of one embodiment of the proposed disclosure similar to FIG. 11 but comprises an additional external terminal.

(16) FIG. 12B shows a circuit schematic representation of one embodiment of the proposed disclosure similar to FIG. 12A and a capacitor connected between the first external control terminal and the aforementioned additional external terminal.

(17) FIG. 13A shows a circuit schematic representation of one embodiment of the proposed disclosure similar to FIG. 11 but comprises an additional external terminal.

(18) FIG. 13B shows a circuit schematic representation of one embodiment of the proposed disclosure similar to FIG. 13A and a capacitor connected between the first external control terminal and the aforementioned additional external terminal.

(19) FIG. 14A shows a circuit schematic representation of one embodiment of the turn-on circuit which comprises a resistor and capacitor.

(20) FIG. 14B shows a circuit schematic representation of another embodiment of the turn-on circuit which comprises a capacitor, a current source and a source/gate connected transistor.

(21) FIG. 15 shows a circuit schematic representation of one embodiment of the turn-on circuit which comprises a resistor.

(22) FIG. 16 shows a circuit schematic representation of one embodiment of the turn-on circuit which comprises a current source and a source/gate connected transistor.

(23) FIG. 17A shows a circuit schematic representation of one embodiment of the on-state circuit which comprises a resistor.

(24) FIG. 17B shows a circuit schematic representation of another embodiment of the on-state circuit which comprises a current source.

(25) FIG. 18A shows a circuit schematic representation of one embodiment of the turn-off circuit which comprises a depletion mode transistor.

(26) FIG. 18B shows a circuit schematic representation of an additional embodiment of the turn-off circuit similar to FIG. 18A which further comprises an enhancement mode transistor.

(27) FIG. 18C shows a circuit schematic representation of an additional embodiment of the turn-off circuit similar to FIG. 18B which further comprises a resistor and capacitor.

(28) FIG. 19A shows a circuit schematic representation of one embodiment of the voltage clamp circuit.

(29) FIG. 19B shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit similar to FIG. 19A which further comprises a capacitor.

(30) FIG. 19C shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit similar to FIG. 19A which further comprises a source-gate connected enhancement mode transistor.

(31) FIG. 19D shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit similar to FIG. 19A which further comprises a temperature compensation circuit.

(32) FIG. 20 shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit which comprises source/gate connected transistors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(33) FIG. 2 illustrates a schematic representation of a cross section of the active area of the proposed disclosure, according to one embodiment of the disclosure. In use the current flows in the active area of the semiconductor device. In this embodiment, the device comprises a semiconductor (e.g. silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. Below the substrate 4 there is a substrate terminal 5. The device includes a first region of a transition layer 3 on top of the semiconductor substrate 4. The transition layer 3 comprises a combination of III-V semiconductor materials acting as an intermediate step to allow the subsequent growth of regions of high quality III-V semiconductor materials.

(34) On top of the transition layer 3 there exists a second region 2. This second region 2 is of high quality III-V semiconductor (for example GaN) and comprises several layers. A third region 1 of III-V semiconductor containing a mole fraction of Aluminium is formed on top of the second region 2. The third region 1 is formed such that a hetero-structure is formed at the interface between the second 2 and third region 1 resulting in the formation of a two dimensional electron gas (2DEG).

(35) A fourth region of highly p-doped III-V semiconductor 11 is formed in contact with the third region 1. This has the function of reducing the 2DEG carrier concentration when the device is unbiased, and is pGaN material in this embodiment. A gate control terminal 10 is configured over the fourth region 11 in order to control the carrier density of the 2DEG at the interface of the second 2 and third region 1. A high voltage drain terminal 9 is arranged in physical contact with the third region 1. The high voltage drain terminal forms an ohmic contact to the 2DEG. A low voltage source terminal 8 is also arranged in physical contact with the third region 1 and also forms an ohmic contact to the 2DEG.

(36) A portion of surface passivation dielectric 7 is formed on top of the fourth region 1 and between the drain terminal 9 and source terminal 8. A layer of SiO.sub.2 passivation 6 is formed above the surface passivation dielectric 7 and source and drain terminals 8, 9.

(37) The device is separated into two cross sections by a vertical cutline. The two cross sections may not be necessarily placed in the same plane. The features described above are on one side (right hand side, for example) of the vertical cutline. This is termed as the active device 205. The other side of the vertical cutline (the left hand side, for example) is termed as the auxiliary device 210, which also comprises a semiconductor substrate 4, a transition layer 3, a second region 2 and a SiO.sub.2 passivation region 6.

(38) A fifth region of III-V semiconductor 17 containing a mole fraction of Aluminium is positioned above the second region 2 in the auxiliary device such that a hetero-structure is formed at the interface between this fifth region 17 and the second region 2. This results in the formation of a second two dimensional electron gas (2DEG) in a region which will be referred to as the auxiliary gate. This AlGaN layer 17 of the auxiliary device 210 can be identical or different to the AlGaN layer 1 in the active device 205. The AlGaN layer thickness and Al mole fraction are critical parameters as they affect the carrier density of electrons in the 2DEG [15].

(39) A sixth region of highly p-doped III-V semiconductor 14 is formed on top of and in contact with the fifth region 17. This has the function of reducing the 2DEG carrier concentration when the auxiliary gate is unbiased. An auxiliary gate control terminal 15 is configured over the sixth region 14 in order to control the carrier density of the 2DEG at the interface of the fifth 17 and second region 2. The auxiliary gate pGaN layer 14 may be identical or different to the active gate pGaN layer 11. Critical parameters which could differ include, but are not limited to, pGaN doping and width along the x-axis (shown in the figure).

(40) An isolation region 13 is formed down the vertical cutline. This cuts the electrical connection between the 2DEG formed in the active device 205 and the 2DEG formed in the auxiliary device 210.

(41) A first additional terminal 16 is arranged on top of and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is also electrically connected (via interconnection metal) to the auxiliary gate control terminal 15 configured over the sixth region (pGaN) 14. The first additional terminal 16 is biased at the same potential as the auxiliary gate terminal 15 of the auxiliary device. A second additional terminal 12 is also arranged on top of and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is electrically connected (via interconnection metal) to the active gate control terminal 10 configured over the fourth region 11 of the active device 205. The interconnection between the second additional terminal 12 of the auxiliary device 210 and the active gate terminal 10 of the active device 205 can be made in the third dimension and can use different metal layers in the process. Note that this interconnection is not shown in the schematic in FIG. 2. A similar but not necessarily identical AlGaN/GaN structure is used in the auxiliary gate.

(42) When the device is in use the auxiliary gate 14, 15 drives the active gate 10, 11. The auxiliary 2DEG layer formed between the first and second additional terminals 12, 16 with the portion under the auxiliary p-GaN gate 14 is controlled by the potential applied to the auxiliary gate terminal 15.

(43) The portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 is depleted when the auxiliary gate terminal 15 and the short-circuited first additional terminal 16 are at 0V. As the auxiliary gate bias is increased (both terminals 15, 16) the 2DEG starts forming under the pGaN gate 14 connecting to the already formed 2DEG layer which connects to the first and second additional terminals 16, 12. A 2DEG connection is now in place between the first and second additional terminals 12, 16.

(44) As the second additional terminal 12 is connected to the active gate 10 the device can now turn on. A positive (and desirable) shift in the device threshold voltage is observed using this structure as not all of the potential applied to the auxiliary gate 15 is transferred to the active gate 10. Part of this potential is used to form the auxiliary 2DEG under the auxiliary gate 15 and only part is transferred to the second additional terminal 12 which is connected to the active gate 10.

(45) The auxiliary gate provides the additional advantage of being able to control the gate resistance of the device more easily. This can be achieved by varying the field plate design or distance between terminals 12 and 15 or 15 and 16. This can be useful in controlling the unwanted oscillations observed due to the fast switching of these devices. Different embodiments of the device can include terminals 10, 15 being either Schottky or Ohmic contacts or any combination of those two.

(46) FIG. 3 shows a circuit schematic representation of one embodiment of the proposed disclosure as shown in the schematic cross section of FIG. 2. The features shown in FIG. 3 carry the same reference numbers as the features in FIG. 2.

(47) FIG. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure in which a low on-state voltage diode is connected in parallel between the drain and the source of the auxiliary transistor, as shown in the schematic 3D illustration in FIG. 4B. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this embodiment a low on-state voltage diode 31 is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. The parallel diode 31 acts as pull-down network during the turn-off of the overall configuration connecting to ground the gate terminal 10 of the active GaN transistor. When a positive bias (known as on-state) is applied to the auxiliary gate 15, the diode 31 will be reverse-biased and zero current will flow through it, leaving unaffected the electrical behaviour of the overall high-voltage configuration. When a zero bias (off-state) will be applied to the auxiliary gate 15 the diode 31 will be forward bias and the turn-off current flowing through it will discharge the gate capacitance of the active transistor, thus enabling the switching off of the overall configuration. In off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. The diode 31 will therefore be designed in such a way that its turn-on voltage will be as low as possible, ideally few mV. FIG. 4B illustrates how the diode 31 could be included monolithically. The diode could be a simple Schottky diode or could be a normal p-n diode. The diode 31 would pull down the active gate 10 during turn-off to the diode Vth, therefore the diode needs to be designed to have as low a threshold voltage as possible. A feature which can achieve this is the use of a recessed anode such that the contact is made directly to the 2DEG as seen in FIG. 4C. FIG. 5 shows a circuit schematic representation of a further embodiment of the proposed disclosure in which the drain (gate) terminal 16 and the source terminal 12 of the auxiliary transistor are available as external gate terminals. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case the external gate terminal is divided into two terminals. Since the gate driver sink output pin can now be connected to the source terminal of the auxiliary transistor directly offering a pull-down path, component 31 in FIG. 4 may (or may not) be omitted.

(48) FIG. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a second auxiliary transistor 34 (could be advantageously low-voltage) is connected in parallel with the first auxiliary transistor where the drain (gate) terminal 16 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case the pull-down network during the turn-off of the overall configuration is a second auxiliary transistor 34.

(49) FIG. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a resistor 41 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the resistor 41 acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the active device. The additional resistor performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12.

(50) FIG. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an additional resistor 42 is added between the source terminal of the auxiliary transistor (drain terminal 12 of the second auxiliary transistor) and source terminal 8 of the active device. Many of the features of this embodiment are similar to those of FIG. 7 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and resistive element 41. In this embodiment, the additional resistive element 42 acts as an additional pull-down network during the active device turn-off. During the active device turn-on and on-state the additional resistance 42 can act as a voltage limiting component to protect the gate terminal of the active device.

(51) FIG. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor 58 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 8 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistive element 42. In this embodiment, the third auxiliary transistor acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 58 performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor.

(52) FIG. 10 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor 59 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 8 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistive element 42. In this embodiment, the third auxiliary transistor acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 59 performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor.

(53) FIG. 11 shows a circuit schematic representation of one embodiment of the proposed disclosure. This embodiment illustrates a power semiconductor heterojunction device comprising (GaN chip) 100 which comprises the high voltage heterojunction transistor (high voltage HEMT, or high voltage transistor) 50, a turn-on circuit 51, a turn-off-circuit 52, an on-state circuit 53 and a voltage clamp circuit 54.

(54) The GaN chip illustrated comprises three terminals: a high voltage terminal, a low voltage terminal and a control terminal.

(55) The GaN chip may be used in switch-mode electronic (power electronics) applications. As such the operation of the GaN chip may be divided into at least four modes of operation: turn-on, on-state, turn-off, off-state.

(56) The GaN chip described herein may comprise additional circuitry connected to the internal gate terminal of the high voltage transistor in order to: optimize the operation of the overall device in the four different modes of operation thus enabling fast and reliable switching operation; and/or increase the gate driving operating range (when the operating range relates to the potential applied to the external control terminal). The wider range for the acceptable control signal applied by the gate driver may be achieved by limiting the maximum voltage signal level that may be applied to the internal gate terminal.

(57) Examples of the internal circuitry of the blocks 51, 52, 53, 54 illustrated in FIG. 11 will be described in this disclosure. It will be appreciated that these examples are not exhaustive, and other variations will be apparent to the skilled person.

(58) FIG. 12A shows a circuit schematic representation of an additional embodiment of the proposed disclosure. The GaN chip 100a in this embodiment is similar to the embodiment illustrated in FIG. 11 but contains an additional external control terminal. The additional external control terminal can allow non-monolithically integrated components to be connected between the first control terminal and the input to the turn-on circuit 51a as illustrated in FIG. 12B.

(59) In FIG. 12B the additional component included is a capacitor 55. Large capacitance values may be difficult to integrate monolithically so might more suitably be included at package or system level. The series capacitor included in the turn-on path i.e. from the gate drive signal (applied to the first control terminal), through the capacitor 55, through turn-on circuit 51a to internal gate terminal can provide an appositely designed transient current through the turn-on path when the external control terminal signal goes from low to high. Furthermore, the design in this embodiment can prevent any significant current through the turn-on path during the period that the control signal is high i.e. the on-state period. Therefore, in this example the comparatively large transient current provided can allow a fast turn-on of the high voltage device however the current during the on-state period can be primarily provided through the on-state circuit 53 which can be optimized to minimise gate driver losses and long-term gate reliability.

(60) FIG. 13A shows a circuit schematic representation of an additional embodiment of the proposed disclosure. The power heterojunction device (GaN chip) 100b in this embodiment is similar to the embodiment illustrated in FIG. 11 but contains an additional external control terminal. The additional external control terminal in this embodiment is operatively connected in the integrated circuit as a third terminal of the turn-on circuit 51b. The additional external control terminal may act as a second input for the turn-on circuit. The first input of the turn-on circuit in this embodiment is operatively connected to the first external control terminal (similar to the embodiment in FIG. 11). The additional external control terminal can allow non-monolithically integrated components to be connected between the first control terminal and the second input to the turn-on circuit as illustrated in FIG. 13B.

(61) In FIG. 13B the additional component included is a capacitor 55. Large capacitance values may be difficult to integrate monolithically so might more suitably be included at package or system level.

(62) FIG. 14A shows a circuit schematic representation of one embodiment of the turn-on circuit 51. In this embodiment the turn-on circuit comprises a capacitor 512 and a resistive element 511 in series.

(63) FIG. 14B shows a circuit schematic representation of another embodiment of the turn-on circuit 51. In this embodiment the turn-on circuit comprises a capacitor 512, a current source 513, 514 and an enhancement mode transistor 515. Current source 513, 514 allows control over the maximum current that can flow through the turn-on circuit, the pre-designed value for this current can be easily adjusted through the choice of resistor 514. Capacitor 512 allows a significant current through the turn-on circuit 51 during the turn-on transient enabling fast turn-on while limiting the current during the on-state period when the potential of the external control terminal and the internal gate terminal reaches a steady state value. To avoid charging up of the capacitor node (i.e. node between transistor 513 and transistor 515) over several switching cycles, a source—gate connected transistor 515 can be introduced as illustrated in this example in order to reset/discharge the capacitor node to the potential of one threshold voltage of the source—gate connected transistor 515. In another embodiment not illustrated here a capacitor may be included in parallel to resistor 514 to provide an additional boost during the turn-on transient.

(64) FIG. 15 shows a circuit schematic representation of one embodiment of the turn-on circuit 51a. In this embodiment the turn-on circuit comprises a resistive element 511a. The operation of this embodiment may be configured to be similar to the turn on circuit shown in FIG. 14A however the capacitor in this embodiment may not be monolithically integrated but rather included at package or system level as illustrated in FIG. 12B.

(65) FIG. 16 shows a circuit schematic representation of one embodiment of the turn-on circuit 51b. In this embodiment the turn-on circuit comprises a current source 513b, 514b and an enhancement mode transistor 515b. The operation of this embodiment may be configured to be similar to the turn on circuit shown in FIG. 14B however the capacitor in this embodiment may not be monolithically integrated but rather included at package or system level as illustrated in FIG. 13B. In another embodiment not illustrated here a capacitor may be included in parallel to resistor 514b to provide an additional boost during the turn-on transient.

(66) FIG. 17A shows a circuit schematic representation of one embodiment of the on-state circuit 53. In this example the on-state circuit 53 comprises a resistive element 531.

(67) FIG. 17B shows a circuit schematic representation of another embodiment of the on-state circuit 53. In this example the on-state circuit 53 comprises a current source. The current source comprises a low voltage depletion HEMT 532 and a resistive element 533.

(68) The on-state circuit is responsible for providing the gate current required to maintain the potential of the internal gate at a desirable potential when the high voltage transistor (active heterojunction transistor) 50 is in the on-state mode of operation. In this GaN chip the current provided by the on-state circuit is primarily composed of the gate leakage current of the high voltage heterojunction transistor and the current through the voltage clamp circuit. Setting the current appropriately is important as it affects the on-state gate driving losses.

(69) FIG. 18A shows a circuit schematic representation of one embodiment of the turn-off circuit 52. In this example the turn-off circuit 52 comprises a depletion mode transistor 521. The drain terminal of the depletion mode transistor is operatively connected to the external control terminal and the source terminal of the depletion mode transistor is operatively connected to the internal gate terminal of the high voltage transistor 50. The gate terminal of the depletion mode transistor is connected to the low voltage terminal of the high voltage transistor 50. When the signal at the external gate control terminal is low (off-state and turn-off mode) the depletion mode transistor provides a low resistance connection between the internal gate and the external control terminal.

(70) In this embodiment, the depletion mode transistor may also act as an additional current path during the turn-on of the high voltage transistor 50. When the external gate control signal goes high the depletion-mode transistor is in saturation mode and provides an additional conduction path for charging the gate-source capacitance of the high voltage transistor 50. As the voltage of the internal gate terminal rises above the threshold voltage of the second depletion mode transistor that conduction path becomes very resistive.

(71) FIG. 18B shows a circuit schematic representation of an additional embodiment of the turn-off circuit 52. In this embodiment an enhancement mode transistor 522 is also used in the turn-off circuit with the drain of transistor 522 connected to the external control terminal and the source and gate of transistor 522 connected to internal gate of high voltage transistor 50.

(72) Transistor 522 acts as a pull-down network during the turn-off of the overall configuration connecting the internal gate terminal of the high voltage GaN transistor 50 to the external control terminal. When a positive bias (on-state) is applied to the external control terminal, source/gate connected transistor 522 will be reverse-biased and negligible current will flow through it, leaving unaffected the electrical behaviour of the overall high-voltage configuration. When a low (close to zero) bias is applied to the external control terminal during turn-off (and off-state) the source/gate connected transistor 522 will become conductive and the turn-off current flowing through it will discharge the gate capacitance of the high voltage transistor, thus enabling the switching off of the overall configuration.

(73) FIG. 18C shows a circuit schematic representation of an additional embodiment of the turn-off circuit 52. In this embodiment a resistor 523 and a capacitor 524 are included to improve the turn-off circuit response during the turn-off transient.

(74) FIG. 19A shows a circuit schematic representation of one embodiment of the voltage clamp circuit 54. The voltage clamp circuit is intended to limit the internal gate to a pre-designed voltage level such that the voltage on the internal gate terminal does not exceed a given value. The voltage clamp circuit comprises two resistors in series 542, 543 forming a potential divider and an actively switched low voltage enhancement mode transistor 541 controlling the potential on the internal gate terminal of the high voltage transistor. The drain of transistor 541 is connected to the internal gate terminal of high voltage transistor 50 and the source of transistor 541 is connected to the low voltage terminal of high voltage transistor 50. The ratio of the resistors in the potential divider can be used to determine the maximum allowable potential on the internal gate terminal.

(75) FIG. 19B shows an embodiment of FIG. 19A with a capacitor 549 in parallel to resistor 543 in order to improve the response time of the voltage clamp circuit.

(76) FIG. 19C shows an embodiment of FIG. 19A in which the voltage response of the voltage clamp circuit may be adjusted by adding one or more source/gate connected HEMTs 550 in the voltage divider. These HEMTs 550 may be connected in series or parallel with either of the resistors 543 or 542.

(77) FIG. 19D shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit 54.

(78) In this embodiment the voltage clamp circuit further comprises an element to compensate or reduce the effect of temperature. This element is a particular embodiment of the voltage divider which is part of the voltage clamp circuit. The first part of the voltage divider may comprise an integrated resistor 543 and the second part of the voltage divider may comprise a current source 544, 545 consisting of a depletion mode HEMT 544 with the source connected to the first terminal of an additional resistor 545 and the gate connected to the second terminal of the resistor. The second part of the voltage divider may further comprise a resistor 542 in parallel to the current source 544, 545.

(79) The first part of the voltage divider may further comprise a similar current source in parallel to the resistor 543 in other examples not illustrated here.

(80) Both parts of the voltage divider will increase the voltage drop at a given current with increasing temperature. But the current sources and resistors change the voltage drop at a dissimilar rate. By designing the sizes of the normally-on HEMTs and the resistances, the output of the voltage divider can be set by the design in such a way that the voltage drop across the pull-down circuit and/or the voltage drop across the auxiliary HEMT has a much smaller temperature dependence.

(81) FIG. 20 shows a circuit schematic representation of an additional embodiment of the voltage clamp circuit 54. In this embodiment the voltage clamp circuit comprises several source/gate connected transistors 546, 547, 548 in series where the source/gate connected terminal is connected to the internal gate terminal of the high voltage transistor 50 and the drain terminal is connected to the low voltage terminal of the high voltage transistor 50.

(82) It will be appreciated that the auxiliary transistor described above in relation to all the embodiments can be a low voltage transistor or a high voltage transistor.

(83) It will also be appreciated that terms such as “top” and “bottom”, “above” and “below”, “lateral” and “vertical”, and “under” and “over”, “front” and “behind”, “underlying”, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied.

(84) Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

REFERENCES

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