Process for producing, from an SOI and in particular an FDSOI type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit

Abstract

An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Claims

1. An integrated circuit, comprising: a substrate of the silicon-on-insulator type comprising a semiconductor film on a buried insulating layer on a carrier substrate; a first zone of said substrate bounded on opposite sides by a first trench isolation and a second trench isolation; a second zone of said carrier substrate bounded on opposite sides by a third trench isolation and a fourth trench isolation and including a portion of said buried insulating layer but wherein no portion of said semiconductor film of said substrate is present in the second zone between the third trench isolation and the fourth trench isolation; a first transistor in said second zone comprising a first gate-dielectric region resting directly on the carrier substrate and formed by said portion of said buried insulating layer, wherein said buried insulating layer is not present in the second zone between a first edge of said portion forming said first gate-dielectric region and an edge of the third trench isolation and wherein said buried insulating layer is not present in the second zone between a second edge of said portion forming said first gate-dielectric region and an edge of the fourth trench isolation and without any presence of the semiconductor film on the first gate-dielectric region.

2. The integrated circuit according to claim 1, further comprising a second transistor in said first zone comprising a second gate-dielectric region resting on said semiconductor film, said second gate-dielectric region being thinner than the first gate-dielectric region.

3. The integrated circuit according to claim 2, wherein the second gate-dielectric region is formed by at least one layer of a first dielectric material and wherein the first transistor further comprises said at least one layer of the first dielectric located on said portion of the buried insulating layer.

4. The integrated circuit according to claim 1, wherein a thickness of said portion of the buried insulating layer in the second zone is thinner than a thickness of the buried insulating layer of the silicon-on-insulator type substrate in the first zone.

5. The integrated circuit according to claim 1, wherein said first transistor located in said second zone is a double-gate transistor comprising: a floating-gate first region separated from the carrier substrate by said portion of said buried insulating layer; and a control-gate second region separated from the floating-gate first region by a gate-dielectric region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting methods of implementation and embodiments, and the appended drawings, in which:

(2) FIGS. 1 to 8 schematically illustrate methods of implementation and embodiments of the invention.

DETAILED DESCRIPTION

(3) In FIG. 1, the reference IC designates an integrated circuit comprising, in a first zone Z1, a fully depleted silicon-on-insulator (FDSOI) substrate comprising a semiconductor film 3, for example having a thickness of 7 nanometers, on a buried insulating layer 2 (BOX), for example having a thickness of 25 nanometers, itself supported by a carrier substrate 1 that may for example be a semiconductor well.

(4) A first MOS transistor T1 is produced in and on the semiconductor film 3 for example in a 28-nanometer CMOS technological node, and is isolated from other components of the integrated circuit by isolating regions RIS for example comprising shallow trench isolations (STIs) extended by deep trench isolations (DTIs).

(5) The transistor T1 comprises a first gate region RG1 insulated from the semiconductor film 3 by a first gate-dielectric region OX1 here comprising a layer of a dielectric material of high relative dielectric constant K, typically higher than 15. By way of indication, the thickness of the layer OX1 is about 4 nanometers.

(6) The gate region RG1 is flanked by insulating lateral regions ESP1, commonly referred to as “spacers” in the art.

(7) The transistor T1 also comprises source S and drain D regions comprising raised portions generally obtained by epitaxy.

(8) In a second zone Z2 of the integrated circuit IC is located a second MOS transistor T2 produced in and on the carrier substrate 1.

(9) More precisely, the transistor T2 comprises a second gate region RG2 insulated from the carrier substrate 1 by a second gate-dielectric region here comprising the dielectric layer OX1 and a portion 200 of the buried insulating layer 2. Thus, the thickness of the second gate-dielectric region of the transistor T2 is larger than the thickness of the first region of the gate dielectric OX1 of the transistor T1.

(10) Typically, to produce a transistor capable of withstanding voltages of 3 to 5 volts, the overall thickness of the second gate-dielectric region is about 8 nanometers with a thickness of the layer 200 of about 4 nanometers.

(11) Conventionally, the second transistor T2 also comprises spacers ESP2 produced on the flanks of the gate region RG2 and source S and drain D regions implanted in the carrier substrate 1.

(12) The residual portion of the buried insulating layer 2 of the FDSOI substrate thus allows, very simply and without consuming the semiconductor film 3, a transistor T2 having a thick gate-dielectric region to be produced.

(13) Moreover, it is also possible, as illustrated in FIG. 2, to produce, on the zone Z2, a plurality of transistors T2, T3 having gate-dielectric regions of different thicknesses, typically obtained with residual portions of the buried insulating layer having different thicknesses.

(14) Thus, as illustrated in FIG. 2, the transistor T3 has a gate-dielectric region comprising a buried-insulating-layer portion 201 having a larger thickness than the portion 200 of the gate-dielectric region of the transistor T2.

(15) Reference is now more precisely made to FIGS. 3 to 7 in order to illustrate one method of implementation of a process according to the invention.

(16) In FIG. 3, the process starts with a silicon-on-insulator substrate comprising the semiconductor film 3 supported by the buried insulating layer 2 (BOX) itself supported by the carrier substrate 1.

(17) The zones Z1 and Z2 of the integrated circuit have here been bounded, in a conventional way known per se, by isolating regions RIS.

(18) Moreover, as is conventionally the case, the semiconductor film 3 is covered with a passivation layer 4, commonly referred to as a “PADOX” in the art, that is intended to protect the surface of the semiconductor film 3 during prior operations, for example the well implantations.

(19) Next, the first zone Z1 is protected with a resist mask 50, then etching GV1 is carried out in the zone Z2 of the integrated circuit so as to remove the subjacent passivation layer 4 and the semiconductor film 3 located in the zone Z2 while leaving behind a residual portion 20 of the buried insulating layer 2 (whose thickness is, in embodiments, less than the thickness of the BOX 2 for example in zone Z1).

(20) After the mask 50 and the passivation layer 4 located in the zone Z1 have been removed, the structure illustrated in FIG. 4 is obtained.

(21) Next, in a conventional way known per se, at least one layer 4 of a gate-dielectric material, for example a material of high relative dielectric constant, is deposited and then a layer 5 of gate material, for example polysilicon and/or a metal, is deposited, without these examples being limiting (FIG. 5).

(22) Next, as illustrated in FIG. 6, the gate regions RG1 and RG2 and the gate dielectric OX1 are patterned using a conventional etch GV2 known per se to define gate stacks.

(23) Next, the insulating lateral regions ESP1 and ESP2 are formed in a conventional way known per se on each side of the gate stacks and, using an etch GV3, that part of the residual portion 20 of the buried insulating layer which is located exterior to the spacers ESP2 is removed, so as to form the buried-insulating-layer portion 200.

(24) As regards the production of the source and drain regions of the transistor of the zone Z2, a plurality of variants are possible.

(25) According to a first variant, the source and drain regions are produced by epitaxy simultaneously to the production of the raised source and drain regions of the transistor of the zone Z1, this then meaning that the source and drain regions of the transistor of the zone Z2 are also raised.

(26) This being so, especially when the transistor of the zone Z2 is a high-voltage transistor, the presence of raised source and drain regions is not in most cases desirable because of the risk of breakdown of the insulating spacer ESP2 between the gate region and these raised source and drain regions, which risks limiting the voltage withstand of the device.

(27) Thus, according to a second variant, the raised source and drain regions of the transistor of the zone Z1 are produced by epitaxy before said residual portion part 20 of the buried insulating layer has been etched. Specifically, this residual buried-insulating-layer portion, which then covers the entirety of the carrier substrate in the zone Z2, blocks the growth of source and drain regions in the zone Z2.

(28) Next, once the raised source and drain regions have been formed in the zone Z1, that part of the residual portion 20 of the buried insulating layer which is located exterior to the spacers ESP2 is removed using the etch GV3 so as to form the buried-insulating-layer portion 200, and then source and drain regions are implanted in the carrier substrate 1.

(29) It is also possible, as a variant, to implant source and drain regions through that part of the residual portion 20 of the buried insulating layer which is located exterior to the spacers ESP2 by adjustment of the implantation energy. Thus, it is not absolutely necessary to etch GV3 these source and drain regions before the implantation.

(30) The invention is not limited to the methods of implementation and embodiments that have just been described but encompasses any variant thereof.

(31) Thus, as illustrated in FIG. 8, it is possible to produce in the zone Z2 of the integrated circuit, a transistor T4 comprising a floating gate, such as those used in non-volatile memory cell such as FLASH or EEPROM cells.

(32) More precisely, as illustrated in FIG. 8, the transistor T4 of the memory cell comprises a floating gate FG separated from the carrier substrate 1 by a first gate oxide 204 that is a residual portion of the buried insulating layer 2.

(33) The transistor T4 moreover comprises a control gate CG separated from the floating gate FG by a dielectric region RD1, for example an oxide-nitride-oxide multilayer.

(34) The two gates and the dielectric regions RD1 and 204 are flanked by lateral spacers ESP4.

(35) The use of a residual layer of buried insulating layer obtained by etching makes it possible to adjust, precisely and very simply, without running the risk of consuming the semiconductor film 3, the thickness of the gate oxide 204, so as for example to obtain a thickness of about 12 nanometers, well suited to erasure using the Fowler Nordheim effect.