BALANCED UNILATERAL FREQUENCY QUADRUPLER

Abstract

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

Claims

1. A frequency multiplier comprising: an input for receiving an input signal; a pair of frequency doublers in quadrature; a third frequency doubler; and a hybrid network connected to the input for feeding the pair of balanced frequency doublers so that the pair of balanced frequency doublers have output signals that are out of phase which are used to drive the third frequency doubler thus producing an output signal at a frequency four times the input signal.

2. The frequency multiplier of claim 1, wherein the frequency doublers each comprise a plurality of quasi-vertical GaAs varactors.

3. The frequency multiplier of claim 2, wherein the number of varactors in each frequency doubler is six.

4. The frequency multiplier of claim 1, wherin each of the pair of frequency doublers is balanced.

5. The frequency multiplier of claim 1, wherein each of the pair of frequency doublers is identical.

6. The frequency multiplier of claim 1, wherein the hybrid network feeds the pair of frequency doublers in phase quadrature.

7. The frequency multiplier of claim 6, wherein the pair of doublers are driven at a fundamental frequency.

8. The frequency multiplier of claim 1, wherein the output signal of the third frequency doubler is a fourth-order harmonic.

9. A frequency multiplier comprising: a first input for receiving an input signal; a first pair of balanced frequency doublers in quadrature; a third frequency doubler; a first hybrid network connected to the first input for feeding the first pair of balanced frequency doublers so that the first pair of balanced frequency doublers have output signals that am out of phase which are used to drive the third frequency doubler thus producing an output signal at a frequency four times the input signal; a second input for receiving the output signal from the third frequency doubler; a second pair of balanced frequency doublers in quadrature; a fourth frequency doubler; and a second hybrid network connected to the input for feeding the second pair of balanced frequency doublers so that the second pair of balanced frequency doublers have output signals that are out of phase which are used to drive the fourth frequency doubler thus producing an output signal at a frequency 16 times the first input signal.

10. The frequency multiplier of claim 9, wherein the frequency doublers each comprise a plurality of quasi-vertical GaAs varactors.

11. The frequency multiplier of claim 10, wherein the number of varactors in each frequency doubler is six.

12. The frequency multiplier of claim 9, wherein each of the first and second pairs of frequency doublers is balanced.

13. The frequency multiplier of claim 9, wherein each of the first and second pairs of frequency doublers is identical.

14. The frequency multiplier of claim 9, wherein the third and fourth hybrid networks respectively feeds the first and second pairs of frequency doublers in phase quadrature.

15. The frequency multiplier of claim 14, wherein the first and second pairs of doublers are driven at a fundamental frequency.

16. The frequency multiplier of claim 9, wherein the output signal of the third frequency doubler is a fourth-order harmonic and the output signal of the fourth frequency doubler is a fourth-order harmonic.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The invention is better understood by reading the following Detailed Description of the Invention with references to the accompanying drawing figures, in which like reference numerals refer to like elements throughout, and in which:

[0015] FIG. 1 is a circuit diagram of a quadrupler circuit architecture embodying the present invention.

[0016] FIG. 2 is a diagram of the geometry of the quadrupler matching and filtering networks for the embodiment of FIG. 1.

[0017] FIG. 3 is a diagram of an input waveguide network to a first-stage doubler according to the present invention.

[0018] FIGS. 4a-4c are diagrams of the three primary stages of the inventive quadrupler, FIG. 4a illustrates the input doubler circuit. FIG. 4b illustrates the output doubler circuit with an intermediate matching stage. FIG. 4c illustrates the output matching circuit and transition to a WR-6 waveguide. All dimensions noted have units of μm.

[0019] FIGS. 5a and 5b graphically illustrate the input and output impedance of the input-stage doubler (FIG. 5a) and the output stage doubler (FIG. 5b). The symbols represent the optimum impedances found from harmonic balance and the solid lines represent the impedances presented by the matching networks of FIGS. 4a-4c.

[0020] FIG. 6 is a diagram of an integrated chip of the inventive quadrupler of FIG. 1.

[0021] FIG. 7 is a planar diagram of a quadrupler housing assembly showing the mounted chip of FIG. 6 and waveguide design features.

[0022] FIG. 8 is a circuit diagram of the embodiment of FIG. 1 arranged in cascade.

[0023] FIG. 9a is a graph showing power and return loss of the inventive quadrupler as a function of bias.

[0024] FIG. 9b is a graph showing output power and efficiency of the inventive quadrupler at a bias of −10 V and input power of 220 mW as a function of input power.

[0025] FIG. 9c is a graph showing output power and return loss of the inventive quadrupler.

[0026] FIG. 10a is a graph illustrating the the output power, conversion gain, and return loss of the input-stage doubler of the inventive quadrupler at an input frequency of 40 GHz and bias Of −10 V as a function of available power.

[0027] FIG. 10b is a graph illustrating output power and return loss of the doubler of the inventive quadrupler as function of frequency.

[0028] FIG. 11a is a graph showing measured change in diode voltage as a function of temperature.

[0029] FIG. 11b is a graph showing estimated anode temperature of the integrated doubler as a function of input power.

DETAILED DESCRIPTION OF THE INVENTION

[0030] In describing preferred embodiments of the present invention illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner to accomplish a similar purpose.

[0031] The present invention presents a frequency multiplier architecture that is intended to address a number of the issues noted above that are frequently encountered in cascaded multipliers. The circuit topology consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadrupler with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicone support membranes. Such quasi-vertical varactors and methods of making same are presented in copending U.S. Patent Application No. (Attorney Docket Number 151093), filed even date herewith and incorporated by reference in its entirety.

[0032] FIGS. 1 and 6 illustrate the basic architecture of a preferred embodiment of the quadrupler circuit 10. The input stage of the multiplier consists of a pair of balanced doublers 12, 14 that are driven through a quadrature: hybrid 16, resulting in two outputs 16, 18 at twice the fundamental input frequency fo and out-of-phase. This circuit topology is often employed for balanced amplifiers and phase-shifters, as any fundamental frequency power reflected from the inputs of the doublers (provided they are identical) is directed to the isolation port, which serves as power “dump.” Consequently, the input source 22 (which may be another multiplier stage in a cascade as shown in FIG. 8) is presented with a march over the bandwidth of the hybrid 16 and is am subject to variations in loading and performance due to changes in the operating conditions of the balanced doublers 12, 14 that it drives. The intermediate outputs 16, 18 at 2fo have the proper phasing to drive a second-stage balanced doubler 24 that bridges the output nodes 15, 17 of the two input-stage doublers, thus yielding a frequency quadrupler 10.

[0033] Design of the quadrupler circuit consists essentially of two steps: determining the proper embedding impedances to present to the varactors of the input balanced doubler driven at the fundamental input frequency of fo (40 GHz) and, similarly, determining the impedances to present to the diodes of the output doubler stage driven at a frequency of 2fo (80 GHz).

[0034] FIG. 2 illustrates the three networks comprising the design: (1) a stepped impedance input matching circuit implemented in (WR-22) waveguide 30. (2) an intermediate matching/filtering network 32, 34 designed to present the proper load impedance to the input doubler and source impedance to the output doubler at 2fo and (3) a matching circuit 36 that couples the output at 4fo to a waveguide probe in the WR-5.1 band.

[0035] The input stage of the quadrupler 10 consists of a pair of identical balanced frequency doublers 12, 14, driven by the TE.sub.10 mode of an input WR-22 (33-50 GHz) waveguide. Design of the doubler is based on an array of anti-series oriented varactors 11, 13 extending across a reduced-height waveguide to suppress excitation of the undesired TM.sub.11 mode which has a field distribution that can couple to the opposing currents generated by the diodes at the second harmonic.

[0036] FIG. 3 shows the detail of the waveguide stepped-impedance network 30 and FIG. 4(a) is a rendering of the top-half of the geometrically-symmetric input stage, detailing the transition from reduced-height waveguide to the diode array and suspended stripline output circuit. The input frequency and available power determine the varactor anode size, substrate doping, epilayer thickness, and the number of diodes required for the doubler, as these parameters directly impact the diode series resistance, breakdown voltage, and onset of velocity saturation. The GaAs epitaxy was selected to have an epitaxial modulation (n) layer 200 nm thick with doping concentration of 2×10.sup.17 cm.sup.−3 and a 1 μm thick highly-doped (5×10.sup.18cm.sup.−3) n-buffer layer. With an anode diameter of 9.6 μm, these parameters yield diodes with zero-bias junction capacitance of 107 fF, reverse breakdown of approximately 9.5 V, and velocity saturation current of 460 mA. Current-voltage measurements of test diodes fabricated with the quadrupler circuit 10 yielded a series resistance for these devices of 0.4 Ω.

[0037] The optimum embedding impedances to present to the diodes in the input-stage doubler were 10+j70Ω for the source impedance 21 at 40 Ghz and 20+j35Ω for the output load at 80 Ghz. The stepped-impedance waveguide transformer of FIG. 3 was designed to present this impedance to each diode 11, 13 of the six-element diode array 12, 14 at 40 GHz.

[0038] FIG. 4a) shows the circuit features of the first-stage doubler geometry 12 or 14 which transitions from reduced-height waveguide to suspended stripline. The symmetry plane is represented as an electric wall for the input fundamental signal, which is essentially unaffected by the stripline circuit to the left of the diode array as it lies along a perfectly conducting boundary. The impedance presented to a diode by the circuit was determined using Ansofts's High-Frequency Structure Site (HFSS) to analyze the structure of FIG. 4(a). For the output second harmonic, a magnetic wall boundary condition is imposed on the symmetry plane and the output circuit designed accordingly to present an impedance of 20+j35Ω to each diode in the array 12 or 14 at 80 GHz. This matching circuit consists of a 74Ω transmission line section and shunt stub 41 of length 400 μm placed 100 μm from the diode array.

[0039] FIG. 5a) shows the impedances presented to the diodes in the input and output stage circuits of FIG. 4(a)as well as the optimum impedances found from harmonic balance.

[0040] The geometry of the intermediate seed(n of the multiplier, extending from the output of the first-stage doubler 12, 14 to the input of the second-stage doubler 24, it shown in FIG. 4(b). This section includes a lowpass filter 42 for the 80 GHz output of the first-stage doubler followed by a stepped-impedance transformer 44 that presents 10+j50Ω to the diodes 46 at the input of the second-stage doubler 24. Because the outputs of the first-stage doublers 12, 14 are out-of-phase, the symmetry plane of FIG. 4(b) is an electric boundary for the input at 80 GHz. This virtual electric boundary extends along the quadrupler output circuit, effectively removing its influence on the input at signal at 2fo (80 GHz).

[0041] As with the input doubler stage, optimum impedances for the diodes of the output doubler stage (10+j50Ω at 80 GHz and 20+j25Ω at 160 GHz) are found using harmonic balance analysis with ADS. The varactor diodes for the output stage make use of the same epitaxy as the input doubter, but the anode diameter is sealed to 8 μm to provide a zero-bias junction capacitance of 75 fF. FIG. 5(b) shows the impedances presented to a diode in the second-stage doubler found from harmonic balance and HFSS simulations of the structure of FIG. 4(b).

[0042] The final step of the quadrupler design consists of transforming the output impedance of the second-stage doubler 24 to the TE 10 mode impedance of the output waveguide, maximizing power coupled to the output WR-5.1 waveguide at 160 GHz. The output-matching network (FIG. 4c) consists of a simple shunt stub and stepped-impedance strip line section that transforms the waveguide probe impedance to 20+j25Ω to the diodes of the doubler array. A thin line (6 μm) edge of the waveguide probe to the beamlead tab 52 provides ground for the diode of the second-stage doubler.

[0043] Final design and optimization of the quadrupler 10 is accomplished with a modular approach where the circuit is partitioned into its primary sections, as described above, and each analyzed using HFSS. Scattering parameters obtained for the matching networks from HFSS are imported into ADS to perform harmonic balance analysis and determine the resulting multiplier performance. This process is iterated, adjusting the geometry of the circuit each time, to bring the impedances presented to the varactors close to their optimum values.

[0044] FIG. 6 shows the final geometry of the quadruple chip resulting from this design process. The chip is a single drop-in unit, approximately 7.5 mm in length, made of 15 μm thick high-resistivity (>10 k Ω-cm) silicon that incorporates three sets 047 balanced doublers 12, 14, 24 (totaling 18 varactor diodes) with associated matching networks 62, 64, 66, and includes gold beamlead tabs 72, 74, 76, 78, 80, and 82 extending from the chip perimeter to accommodate alignment impedances.

[0045] The beamlead tabs 74, 74′ and 80, 80′ protruding from the circuit at the two input-stage doublers 12 and 14 and the beamlead tab 72 protruding from WR-5.1 output probe 102 provide grounding and support the circuit as it is clamped in the split-block seam 104 of the housing 100 (FIG. 7) during assembly. Two additional beamleads 76 and 82 protrude from hairpin bias chokes 110 and 112 and are bonded to quartz-supported filters 114 and 116 to provide DC bias to the doubler arrays.

[0046] Fabrication of the multiplier chip shown in FIGS. 1 and 6 is based on the inventors' quasi-vertical diode architecture and fabrication process described in their co-pending U.S. patent application. (Atty Docket 151093), which claims the benefit of U.S. Provisional Application No. 62/043,698, filed Aug. 29, 2014, and in Chapter 4 of Alijabban, N. (2014), “Submillimeter-Wave Quasi-Vertical GaAs Schottky Diodes Integrated on Silicon Membranes” (retrieved from http://libra.virginia.edu/catalog/libraoa: 7744), all of which are incorporated herein by reference in their entireties.

[0047] This quasi-vertical diode geometry has an integrated bottom ride ohmic contact that is bonded to a host substrate. More specifically, its geometry includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin (1 μm or less) mesa of semiconductor material (e.g., GaAs) with appropriate epilayers for the diode application, including a bottomside highly-doped layer, a bottomside ohmic contact that lies directly below the anode, a thin bonding layer below the ohmic contact, and a host substrate (such as high-resistivity silicon or diamond) onto which the diode material has been attached.

[0048] The bottom ohmic contact is characterized in that it (1) can be placed in close proximity to the anode contact, (2) allows current to flow through the bulk semiconducting material rather than along the surface, (3) can be bonded to a variety of substrate materials to address thermal grounding or loss issues, and (4) remains compatible with integration into planar circuit architectures.

[0049] In broad terms, the fabrication process includes the following steps (1) preparation of a semiconductor wafer for processing (including initial etching of material to expose a highly-doped (n++) epilayer, (2) deposition of metals and annealing to form the ohmic contact art the bottom side of the semiconductor wafer to create a diode wafer, (3) application of an adhesive bonding layer (such as spin-on-glass) to the host substrate, (4) thermal compression bonding of the diode wafer 300 and host substrate wafer, with the ohmic contact side of the diode wafer 300 facing the host substrate wafer to form a composite wafer, (5) etching and formation of diode mesas to isolate devices on the host substrate, (6) lithography and formation of topside anode contact and external circuitry on the host substrate wafer.

[0050] A keys step of the process is transfer of the GaAs epitaxy to a silicon-on-insulator (SOI) substrate that serves as the final carrier chip for the diodes and their associated circuitry. After initial formation of the device ohmic contacts, the diode epitaxy is bonded, ohmic contact-side-down, to the SOI substrate. Following this step, most of the GaAs is etched from the wafer, leaving only mesas for fabrication of the diodes. The remaining features of the diodes and multiplier circuits (anode, contact finger and cathode metallization) are fabricated using standard lithographic, metal deposition, and etching processes.

[0051] Following the diode processing steps, the wafer is bonded topside-down to a temporary carrier wafer, revealing the backside silicon handle of the SOI. This “handle” silicon is removed through reactive ion etching to the buried oxide layer, which acts as an etch stop. Buffered hydrofluoric (HF) acid is used to etch the oxide, leaving the multiplier circuits on a thin (15 μm) high-resistivity silicon membrane bonded to the carrier. A backside reactive-ion “extents” etch is used to separate the multiplier chips and define their geometry. The final step in the process is removal of the temporary carrier wafer, releasing the individual chips.

[0052] With reference to FIG. 7, the housing 100 for the quadrupler circuit 10 is fabricated as an E-plane split-block assembly from gold-plated aluminum using standard milling methods. The housing includes a coupler (e.g., a WR-22 3-dB stepped branchline coupler) to provide in-phase and quadrature inputs to the quadrupler chip waveguide, sections, and channels to accommodate quartz-supported filters for bias connections. External bias is supplied to the chip through low-profile GPPO connectors. The input 111 and isolation port 112 of the multiplier are configured to mate with the waveguides.

[0053] Beamlead tabs protruding from the chip at the two input-stage doublers and the output provide grounding and support the circuit as it is clamped in the split-block seam of the housing during assembly. Two additional beamleads protrude from hairpin bias chokes and are bonded to quartz-supported filters to provide DC bias to the diode arrays. The multiplier 10 can be implemented in either planar circuit, quasi-optical, or waveguide media (as illustrated in the previous figures) and is amenable to integrated fabrication technology.

[0054] Measurement of the quadrupler 10 was done at the University of Virginia and repeated at Virginia Diodes, Inc., to ensure consistent results were obtained.

[0055] FIG. 9(a) shows the measured output power of the quadrupler at 160 GHz as the (reverse) bias voltage to the diodes is varied. With 220 mW of available power at the input, a peak output power of 62 mW is obtained at a bias of −10 V. FIG. 9(a) also shows the return loss from the quadrupler, determined from the ratio of power measured at the isolation port to the available power at the input, as bias is varied. Below a bias voltage of −6 V, no output power was measured. The quadrupler output power at 160 GHz and bias of −10 V as a function of input power is shown in FIG. 9(b). Over the 175-325 mW range of input power applied, the quadrupler efficiency remained approximately 25% or better, with a maximum efficiency near 30% at an input power of 240 mW. At an applied input power of 325 mW, an output of 79 mW was obtained at 160 GHz.

[0056] FIG. 9(c) shows the multiplier output power and return loss over the 142-172 GHz output frequency range, corresponding to the 36-43 GHz bandwidth of the input amplifier. These measurements were performed with 220 mW of input power and a voltage bias of −10 V. The 3 dB output bandwidth of the quadrupler as approximately 20 GHz, or 13%. The three sets of power data presented in FIG. 9c correspond to separate assemblies of the quadrupler, each using different chips, illustrating a high degree of repeatability and consistency in performance resulting from the integrated architecture of the multiplier.

[0057] The RF performance of the doubler is summarized in FIGS. 10(a) and 10(b). A peak doubler efficiency of 62% (conversion gain of −2.2 dB) was achieved at 80 GHz for an input available power of 100 mW and bias of −10 V. The 3 dB bandwidth of the doubler (FIG. 10(a)) is approximately 18% and a maximum output power of 113 mW was achieved at 80 GHz with at input of 380 mW (the upper power limit of the Spacek amplifier). Above 400 mW of applied input power, the voltage swing across the diodes is predicted, from harmonic balance analysis, to exceed 9.5 V breakdown voltages of the diodes.

[0058] To estimate the operating temperature of the varactors comprising the doubler, the current-voltage characteristic of the diodes was used as an in-situ thermometer. Initially, a set of DC current-voltage measurements of the six-element diode array were taken at temperatures ranging from 25° C. to 90° C. These measurements were done with the doubler chip placed on a temperature-controllable hot plate, after the diodes were allowed to reach thermal equilibrium. Data taken from these measurements served as a calibration to permit the temperature of the diodes to be estimated when subjected to RF power. FIG. 11(a) shows the change in voltage drop across the diodes found from this measurement, at a fixed current bias of 100 μA and as a function of applied temperature. The estimated temperature of the diodes in the doubler circuit as a function of available input power at 40 GHz is provided in FIG. 11(b). For this measurement, the doubler was pumped with the input RF signal at a fixed power for several seconds. Afterwards, the input power source was removed, a current bias of 100 μA was immediately applied, and the diode voltage was sampled and monitored over a time interval of 50 ms. Using the measured voltages, extrapolating, and applying the calibration data of FIG. 11(a) allowed the temperature of the varactors to be estimated. Although this method cannot give temperature estimates for the individual diodes in the array, it does provide a measure of the approximate temperature rise of the devices when subjected to high input power levels. When driven at 100 mW for peak efficiency, the temperature of the varactors is estimated from these measurements to be 35° C., approximately 30° C. lower than that calculated for the substrateless 100-200 GHz doubler and over 100° C. cooler than the GaAs membrane multiplier investigated in [101], for the same input power.

[0059] An aspect of various embodiments of the present invention may provide a number of novel and nonobvious features, elements and characteristics, such as but not limited thereto: (1) incorporation of a hybrid coupler 16 to drive a pair of balanced doublers 12, 14 in phase quadrature combined with (2) integration of an output balanced doubler 24 that bridges the output nodes 15, 17 of the pair of input balanced doublers.

[0060] An aspect of various embodiments of the present invention may be utilized for a number of products and services. Frequency multipliers are currently the most widely used and important technology for realizing solid-state frequent sources above 100 GHz. Multipliers are used as local oscillators for high-frequency receivers, frequency upconverters in commercial network analyzer extension modules (currently marked by a number of companies), and as sources for spectroscopic measurements.

[0061] Modifications and variations of the above-described embodiments of the present invention are possible, as appreciated by those skilled in the art in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described. For example, as with the 40/160 GHz quadrupler, the input of cascaded balanced multipliers, such as that shown in FIG. 8 would not load the driving stages and eliminates issues associated with cascading multipliers in a large chain. The reflected power from mismatches between stages would be terminated, allowing one to reach the 640 GHz and beyond with fewer multiplier blocks (or several chips integrated into a single block).

[0062] The devices, systems, compositions and computer readable medium, and methods of various embodiments of the invention disclosed herein may utilize aspects disclosed in the following references, applications, publications and patents and which are hereby incorporated by reference herein in their entireties (and which are not admitted to be prior art with respect to the present invention by inclusion in this section):

PUBLICATIONS

[0063] J. W. Gewartowski, “Unilateral Frequency Multiplier Circuit” Proceedings of the IEEE pp. 1749-1750, December 1964.

[0064] R. D. Brooks, J. W. Gewartiowski, “Unilateral 6-GHz 2 ½-Watt Varactor Quadrupler,” IEEE Trans. Solid-State Circuits VOL. SC-3, NO. 2, JUNE 1968, pp. 182-189.

[0065] N. Erickson, “High efficiency submillimeter frequency multipliers,” in IEEE MTT-S Int. Microwave Symp. Dig., 1990, pp. 1301-1304,

[0066] N. Erickson, B. Rizzi, and T. Crowe, “A high-power doubler for 174 GHz using a planar diode array,” in Proc. 4th Int. Space THz Tech. Symp., March 1993, pp. 287-296.

[0067] D. W. Porterfield, et al, “A High-Power Fixed-Tuned Millimeter-Wave Balanced Frequency Doubler,” IEEE Trans. Microwave Theory and Tech. vol. 47, no. 4, pp. 419-425, 1999.

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