Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure which is arranged above the first transistor structure and which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure of the at least one CFET element, and a power routing line arranged above the second transistor structure of the at least one CFET element. The power routing line is electrically connected to the source and/or drain structure of the second transistor structure from the top. The at least one CFET element further has a tap connection structure which is arranged to electrically connect the power rail with the source and/or drain structure of the second transistor structure. The tap connection structure is arranged to bypass the first transistor structure on one side.

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In one embodiment, a method for manufacturing a semiconductor device may comprise the steps of: growing a stack layer by alternately stacking sacrificial layers and channel regions on a substrate; forming a sacrificial poly gate on the stack layer; forming inner spacers and side spacers on side surfaces of the sacrificial layers and side surfaces of the sacrificial poly gate; and heat treating the inner spacers or the side spacers in a chamber set to a predetermined process pressure and a predetermined process temperature.

A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.

A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/ C.

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

A method for forming a semiconductor structure includes: providing a substrate, in which a gate structure is formed on the substrate; forming first side walls covering side surfaces of the gate structure, in which the first side walls have a first preset thickness in a direction parallel to a plane of the substrate; performing first ion implantation on the substrate on both sides of the gate structure exposed to the first side walls; removing a part of the first side walls to form second side walls, in which the second side walls have a second preset thickness in the direction parallel to the plane of the substrate; and performing second ion implantation on the substrate on both sides of the gate structure, in which doping types of the first ion implantation and the second ion implantation are different.