A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

An integrated circuit device includes a substrate, a fin-type active area on the substrate, a nanosheet stacked structure including a plurality of nanosheets, a gate electrode surrounding the nanosheet stacked structure on the fin-type active area, and a source/drain region connected to one end of the plurality of nanosheets on the fin-type active area, wherein the source/drain region includes a first source/drain layer in contact with the upper surface of the fin-type active area and side surfaces of the plurality of nanosheets, a second source/drain layer covering the first source/drain layer, a third source/drain layer covering part of the second source/drain layer, and a fourth source/drain layer covering the second source/drain layer and the third source/drain layer.

An integrated circuit device includes: a fin-type active area extending in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active area; a source/drain area arranged on the fin-type active area; a gate dielectric layer disposed on the gate line; a source/drain contact arranged on the source/drain area; a via contact integrally connected to the source/drain contact and protruding in a vertical direction; a gate contact plug integrally connected to the gate line and protruding in the vertical direction; a first wiring layer electrically connected to the via contact and the gate contact plug; and a via rail connected to the first wiring layer, and extending in the first horizontal direction at a vertical level that is lower than a vertical level of the first wiring layer.

A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

Disclosed is a semiconductor device including a substrate and a wiring structure on the substrate. The wiring structure includes a first interlayer dielectric layer on the substrate and including a plurality of first metal lines, and a second interlayer dielectric layer on the first interlayer dielectric layer and including a via structure connected to the first metal line. The via structure includes a first via part and a second via part on the first via part. A first width of the first via part is less than a second width of the second via part.

A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.