A semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer and having a side wall and a bottom wall, a field plate electrode formed in the trench, a gate electrode formed in the trench, and an insulation layer that isolates the field plate electrode and the gate electrode from each other and covers the side wall and the bottom wall in the trench. The semiconductor layer includes a drift region and a body region formed on the drift region. An interface of the drift region and the body region lies between a lower end position of the gate electrode and a reference position that is located upward from the lower end position by the thickness of the gate electrode in the depth direction.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

A semiconductor device includes a substrate including a fin-type active area and a device separation layer configured to cover both sidewalls of the fin-type active area, a pair of nanosheet stacks each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack, an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack, a nanosheet separation wall arranged between each of the pair of nanosheet stacks and extending in a first horizontal direction, and a pair of gate lines extending on the pair of nanosheet stacks in a second horizontal direction, wherein the nanosheet separation wall separates respective lower nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction.

Semiconductor device structures are provided. The semiconductor device structure includes a semiconductor substrate with an original semiconductor surface and an active region, a STI region surrounding the active region, a transistor formed based on the active region and including a gate structure, a first conductive region, a second conductive region and a channel region between the first and second conductive regions, an interconnection structure extending beyond the transistor, and a connecting plug electrically connecting the interconnection structure to the first conductive region of the transistor. The first conductive region includes an epitaxial semiconductor material. The interconnection structure is disposed under the original semiconductor surface and within the STI region.

Embodiments of the present disclosure include a transistor with a vertical drift region and methods for forming the transistor. The transistor may include a well region of a first conductivity type, a gate region disposed above the well region, and a drift region of a second conductivity type, different from the first conductivity type. The drift region may have a lateral portion disposed above a portion of the well region and laterally adjacent to a semiconductor channel in the well region. The drift region may also have a vertical portion extending vertically from the lateral portion of the drift region.

Systems, methods, and apparatus are provided for bifurcated access line contacts. Horizontally oriented access devices each have a first source/drain region and a second source drain region separated by channel regions. Gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from channel regions by gate dielectrics. Horizontally oriented storage nodes can be electrically coupled to the second source/drain regions of the horizontally oriented access devices. A staircase structure at each level on a periphery of the array of vertically stacked memory cells and a plurality of separate vertical connections each connected to a different one of a plurality of horizontally oriented access lines formed with the GAA structures on each level of the array.

In a semiconductor integrated circuit device, a standard cell includes: an active region forming the channel, source, and drain of a transistor; and a power line formed on the back side of the transistor. A first region in the active region is connected to the power line through a via. A nanosheet contiguous with the active region is formed on a cell boundary. A gate interconnect, which is orthogonal to the nanosheet in planar view, is electrically connected to the first region.

A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.

The present inventive concept provides a method of manufacturing an oxide transistor, the method comprising: a step of forming a first channel layer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen; a step of forming a spacer on the first channel layer by supplying a gas containing gallium (Ga) and supplying a gas containing oxygen; and a step of forming a second channel layer on the spacer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen, and an oxide transistor made by the method.