A thin film transistor and a preparation method therefor, an array substrate and a display apparatus. The thin film transistor comprises an active layer (4), an etched barrier layer (5) disposed on the active layer (4), and a source and drain (6) disposed on the etched barrier layer (5). The source and drain (6) are disposed on a same layer in a spaced manner. First via holes (7) are formed in the etched barrier layer (5), second via holes (8) are formed in positions in the active layer (4) corresponding to the first via holes (7). The source and drain (6) are connected to the active layer (4) through the first via holes (7) formed in the etched barrier layer (5) and the second via holes (8) formed in the active layer (4). Because two second via holes are formed in the active layer, a design value L1 of the channel region length of the active layer is shortened and a metal oxide semiconductor array substrate with a narrow channel is formed and the charge rate is high, which helps to improve the display effect.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

An array substrate includes a substrate (100) having a plurality of sub-pixel regions. Each sub-pixel region includes: a switching element (1) disposed on the substrate, a conductive planar layer (113) disposed on the switching element (1), and a pixel electrode (111) disposed on the conductive planar layer (113), the pixel electrode (111) being electrically connected to the output electrode (105) of the switching element (1). Such array substrate improves the instability of the device caused by stress between materials, enhances the long-term stability of the device, and simplifies the manufacturing process.

In a touch screen substrate and a method of manufacturing the same, the touch screen substrate includes a base substrate, a light blocking pattern, a first sensing element and a first switching element. The light blocking pattern includes an inorganic layer formed on the base substrate and a light blocking layer formed on the inorganic layer, the light blocking layer transmitting an infrared light and absorbing a visible light. The first sensing element is formed on the light blocking pattern and senses the infrared light. The first switching element is electrically connected to the first sensing element. Thus, an undercut may be prevented from being formed at a lower portion of the light blocking pattern, and an adhesive strength between the light blocking pattern and the base substrate may be enhanced.

Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines disposed on the base substrate and configured to define a plurality of pixel regions; pixel electrodes and common electrodes disposed in each pixel region and arranged in different layers; and shielding electrodes being at least formed in regions corresponding to the data lines on the base substrate, being arranged in different layers from the common electrodes, and being not electrically connected with the pixel electrodes and the common electrodes.

A display device according to an embodiment includes a substrate, first assembly wiring and second assembly wiring that are spaced apart from each other on the substrate and each include a conductive layer and a clad layer on the conductive layer, a structure that is in contact with the second assembly wiring and has a reverse taper shape, a planarization layer that is disposed on the first assembly wiring and the second assembly wiring and has an opening, and a light emitting device that is disposed inside the opening and has a first electrode overlapping the first assembly wiring and the second assembly wiring, wherein the structure is disposed to cover a portion of an upper surface of the conductive layer of the second assembly wiring.

A display panel and a display device are provided. The display panel includes sub-pixels, data lines and gate lines. The sub-pixels include pixel circuits connected to the data lines and the gate lines. The display panel includes display subregions and selection signal line groups in one-to-one correspondence, each display subregion includes at least two sub-pixels, each selection signal line group includes selection signal lines, and the selection signal lines corresponding to different display subregions are insulated from each other; the pixel circuit includes a transistor in which an active semiconductor layer includes a first part and a second part, the first part overlaps with the gate line electrically connected with the transistor, and the second part overlaps with at least one selection signal line, and the gate line and the selection signal line are both configured to turn on the transistor upon being input with a turn-on voltage.