The present invention provides a quantum dot light emitting element, a manufacture method thereof and a liquid crystal display device. The quantum dot light emitting element comprises a substrate, an anode, a Hole Injection and Hole Transporting Layer, a quantum dot light emitting layer, an Electron Injection and Electron Transporting layer and a cathode, and the anode is located on the substrate, and the anode and the cathode are located at the same side of the substrate, and are opposite and separately located, and the Hole Injection and Hole Transporting Layer, the quantum dot light emitting layer and the Electron Injection and Electron Transporting layer are sequentially sandwiched between the anode and the cathode, and one surface of the Hole Injection and Hole Transporting Layer is connected with the anode, wherein the Electron Injection and Electron Transporting layer comprises water/alcohol soluble conjugated polymer.

A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.

A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes: a coating step to coat a liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a UV irradiating step to form a UV-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the UV-irradiated coating films, after forming the plurality of UV-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the UV irradiating step.

A battery having desired characteristics and a method of charging and discharging a battery are provided. A battery according to an embodiment of the present invention includes: a first electrode layer (6); a second electrode layer (7); and a charging layer (3) including an n-type metal oxide semiconductor and an insulating material, a charge voltage generated between the first electrode layer (6) and the second electrode layer (7) being applied to the charging layer (3). On a surface of the charging layer (3), a region in which the second electrode layer (7) is formed is sandwiched between regions in which the second electrode layer (7) is not formed.

Subject matter disclosed herein may relate to fabrication of layered correlated electron materials (CEMs) in which a first group of one or more layers may comprise a first concentration of a dopant species, and wherein a second group of one or more layers may comprise a second concentration of a dopant species. In other embodiments, a CEM may comprise one or more regions of graded concentration of a dopant species.

A method for preparing semiconductor nanocrystals is disclosed. The method comprises adding a precursor mixture comprising one or more cation precursors, one or more anion precursors, and one or more amines to a ligand mixture including one or more acids, one or more phenol compounds, and a solvent to form a reaction mixture, wherein the molar ratio of (the one or more phenol compounds plus the one or more acids plus the one or more amine compounds) to the one or more cations initially included in the reaction mixture is greater than or equal to about 6, and heating the reaction mixture at a temperature and for a period of time sufficient to produce semiconductor nanocrystals having a predetermined composition. Methods for forming a buffer layer and/or an overcoating layer thereover are also disclosed. Semiconductor nanocrystals and compositions including semiconductor nanocrystals of the invention are also disclosed. In certain embodiments, a semiconductor nanocrystal includes one or more Group IIIA and one or more Group VA elements.

Subject matter disclosed herein may relate to fabrication of layered correlated electron materials (CEMs) in which a first group of one or more layers may comprise a first concentration of a dopant species, and wherein a second group of one or more layers may comprise a second concentration of a dopant species. In other embodiments, a CEM may comprise one or more regions of graded concentration of a dopant species.

IR emission devices comprising an array of polaritonic IR emitters arranged on a substrate, where the emitters are coupled to a heater configured to provide heat to one or more of the emitters. When the emitters are heated, they produce an infrared emission that can be polarized and whose spectral emission range, emission wavelength, and/or emission linewidth can be tuned by the polaritonic material used to form the elements of the array and/or by the size and/or shape of the emitters. The IR emission can be modulated by the induction of a strain into a ferroelectric, a change in the crystalline phase of a phase change material and/or by quickly applying and dissipating heat applied to the polaritonic nanostructure. The IR emission can be designed to be hidden in the thermal background so that it can be observed only under the appropriate filtering and/or demodulation conditions.

A method for manufacturing an emitter comprises providing a semiconductor substrate having a main surface, the semiconductor substrate comprising a cavity adjacent to the main surface. A portion of the semiconductor substrate arranged between the cavity and the main surface of the semiconductor substrate forms a support structure. The method comprises arranging an emitting element at the support structure, the emitting element being configured to emit a thermal radiation of the emitter, wherein the cavity provides a reduction of a thermal coupling between the emitting element and the semiconductor substrate.

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.