Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An n.sup.th photoelectric conversion unit segment is formed of an n.sup.th charge storage electrode segment, an n.sup.th insulating layer segment and an n.sup.th photoelectric conversion layer segment. As n increases, the n.sup.th photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to N.sup.th photoelectric conversion unit segment.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

The present disclosure relates to an electrostatic protection device including an SCR and a manufacturing method thereof. The electrostatic protection device includes a third N+ doped region across an N-type well region and a P-type well region, and a third P+ doped region adjacent to the third N+ doped region. Each of the third N+ doped region and the third P+ doped region has a high doping concentration. In a case that Zener breakdown occurs in a PN junction structure between the third N+ doped region and the third P+ doped region, the SCR is triggered to form a discharge current path. The present disclosure can reduce a trigger voltage of an electrostatic protection device including an SCR, and can provide electrostatic protection devices having different trigger voltages, with high stability and high robustness.

In an uninterruptible power supply device, a control module includes a thyristor unit, a control unit, and a housing that accommodates the thyristor unit and the control unit, in which the thyristor unit and the control unit are arranged in a front-rear direction intersecting a left-right direction in the housing of the control module.

In an uninterruptible power supply device, a control module includes a thyristor unit, a control unit, and a housing that accommodates the thyristor unit and the control unit, in which the thyristor unit and the control unit are arranged in a front-rear direction intersecting a left-right direction in the housing of the control module.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

A semiconductor controlled rectifier is provided. The rectifier includes an anode, a cathode, and a well including a first contact and a second contact. The anode is positioned between the first and second contacts, the first contact is arranged to provide a first current flow path from the first contact to the cathode via the anode, and the second contact is arranged to provide a second current flow path from the second contact to the cathode via the anode.

A bidirectional thyristor device (1) comprising a semiconductor body (2) extending between a first main surface (21) and a second main surface (22), is provided wherein a first main electrode (31) and a first gate electrode (41) are arranged on the first main surface and a second main electrode (32) and a second gate electrode (42) are arranged on the second main surface. The first main electrode comprises a plurality of first segments (310) that are spaced apart from one another, wherein at least some of the first segments are completely surrounded by the first gate electrode in a view onto the first main surface. The second main electrode comprises a plurality of second segments (320) that are spaced apart from one another, wherein at least some of the second segments are completely surrounded by the second gate electrode in a view onto the second main surface.