In accordance with an example embodiment of the present invention, a device is disclosed. The device comprises: a sensing region comprising an active material and two or more electrodes in electrical contact with the active material; and a switching region providing control over the sensing region, the switching region comprising an active material and two or more electrodes in electrical contact with the active material. The switching region and the sensing region share one electrode, and the switching region and the sensing region share at least part of the active material. A method and apparatus for producing the device are also disclosed.

A static random access memory device includes two body contacts and two resistive-switching devices. The body contacts are disposed in a wafer and are exposed from a back side of the wafer, wherein the body contacts electrically connect a static random access memory cell through a metal interconnect in the wafer. The resistive-switching devices connect the two body contacts respectively from the back side of the wafer. A method of forming a static random access memory device is also provided in the following. A wafer having two body contacts exposed from a back side of the wafer and a metal interconnect electrically connecting a static random access memory cell to the body contacts is provided. Two resistive-switching devices are formed to connect the two body contacts respectively from the back side of the wafer.

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing and/or bromine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing and/or bromine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.

A semiconductor structure includes a front side and a back side opposite to the front side, at least a transistor device formed on the front side of the substrate, and an adjustable resistor formed on the back side of the substrate. The adjustable resistor includes at least a phase change material PCM layer.

A phase-change memory element is provided. The phase-change memory element may include an electrode; a phase-change material that contacts the electrode; a first conductor that contacts the phase-change material; and a second conductor that contacts the phase-change material. The second conductor may be electrically connected to the first conductor only through the phase-change material, and each of the first and second conductors may be electrically connected to the electrode only through the phase-change material.

A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region.

A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Some embodiments relate to an integrated circuit including a memory cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A data storage layer is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the data storage layer and is in direct electrical contact with a lower surface of the upper metal layer.

A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.