A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an interlayer insulating film via a metal block such as Cu. In the wiring structure using the CNTs at the via part and the graphene at the wiring part, it is thereby possible to obtain the wiring structure with high reliability enabling a certain electrical connection between the CNTs and the graphene with a relatively simple configuration.

Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.

A semiconductor device includes first conductive lines and first and second insulation patterns on a substrate, first structures spaced apart from each other on the first conductive lines, a variable resistance pattern on the first structures, and a second electrode on the variable resistance pattern. The first conductive lines extend in a first direction. The first structures include a switching pattern and a first electrode sequentially stacked. The first insulation pattern fills a space between the first structures in a second direction and the first insulation pattern has a first top surface higher than a top surface of the first structures. The second insulation pattern fills a space between the first structures in the first direction, and the second insulation pattern has a second top surface higher than a top surface of the first structures. The variable resistance pattern fills an opening defined by the first and second insulation patterns.

An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.

Some embodiments include a device having a conductive material, a metal chalcogenide-containing material, and a region between the metal chalcogenide-containing material and the conductive material. The region contains a composition having a bandgap of at least about 3.5 electronvolts and a dielectric constant within a range of from about 1.8 to 25. Some embodiments include a device having a first electrode, a second electrode, and a metal chalcogenide-containing material between the first and second electrodes. The device also includes an electric-field-modifying region between the metal chalcogenide-containing material and one of the first and second electrodes. The electric-field-modifying region contains a composition having a bandgap of at least about 3.5 electronvolts having a low dielectric constant and a low conduction band offset relative to a workfunction of metal of the metal chalcogenide-containing material.