A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.

A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.

A composition of matter consisting primarily of a stabilizing element and a transition metal oxide, wherein the transition metal oxide is an anti-ferromagnetic Mott insulator with strong spin orbit interactions, and the composition of matter has a canted crystal structure.

An integrated neuron circuit structure comprising at least one thin-film resistor, one Metal Insulator Metal capacitor and one Negative Differential Resistance device.

A vanadium dioxide (VO.sub.2)-based threshold switch device exhibiting current-controlled negative differential resistance (S-type NDR), an electrical oscillator circuit based on the threshold switch device, a wafer including a plurality of said devices, and a method of manufacturing said device are provided. The VO.sub.2-based threshold switch device exhibits volatile resistance switching and current-controlled negative differential resistance from the first time a sweeping voltage or voltage pulse is applied across the device without being treated with an electroforming process. Furthermore, the device exhibits substantially identical switching characteristics over at least 10.sup.3 switching operations between a high resistance state (HRS) and a low resistance state (LRS), and a plurality of threshold switch devices exhibits a threshold voltage V.sub.T spreading of less than about 25%. The threshold switch device may be included in an oscillator circuit to produce an astable oscillator that may serve as a functional building block in spiking-neuron based neuromorphic computing.

A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.