The present disclosure discloses a semiconductor device and a fabrication method thereof. In the method, firstly etching a substrate in a first device region to form at least one first trench and then etching the substrate in both first device region and second device region to form at least one first isolation trench at the positions corresponding to the at least one first trench and form at least one second isolation trench in the second device region. Herein a depth of the first isolation trench is larger than that of the second isolation trench.

Examples are disclosed relate to using an inhibitor with a silicon oxide ALD deposition process to refill recesses in STI regions. One example provides a method of processing a substrate. The method comprises depositing an inhibitor on the substrate, wherein a concentration of the inhibitor on a gate structure of the substrate is greater relative to the concentration of the inhibitor on a recessed shallow trench isolation (STI) region of the substrate. The method further comprises depositing a layer of silicon oxide on the substrate, the inhibitor inhibiting growth of the layer of silicon oxide such that the layer of silicon oxide is thicker on the recessed STI region and thinner on the gate structure.

An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

A method for manufacturing a semiconductor structure is provided. A first mask layer and a photoresist layer are formed over a substrate, wherein photosensitivities of the photoresist layer and the first mask layer are different. A first and a second opening are formed, wherein the first mask layer overlapped by the second opening is degraded to form a second mask layer. The substrate exposed by the first opening is partially removed to form a first recess of the substrate. The second mask layer is removed to form a third opening through the first mask layer. A first dielectric layer is formed, wherein the first dielectric layer fills the first recess and the third opening and covers the substrate overlapped by the third opening. A patterning operation is performed on the substrate using the first dielectric layer as a mask, and a second recess of the substrate is thereby formed.

A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

A semiconductor structure manufacturing method includes: providing a substrate and etching the substrate to form first trenches; filling each of the first trenches with an oxide layer having a top surface not lower than that of the substrate; etching regions, adjacent to side walls of the first trench, in the oxide layer downwards to form second trenches, wherein a depth of the second trench is less than a depth of the first trench and a width of the second trench is less than half of a width of the first trench; and forming supplementary layers in the second trenches.

A manufacturing method for a semiconductor device, includes: forming a first gate structure and a second gate structure on a substrate; forming a deep trench isolation (DTI) hard mask on the first and second gate structures; forming a deep trench isolation disposed between the first gate structure and the second gate structure; depositing a first undoped oxide layer in the deep trench isolation; performing a first etch-back process on the first undoped oxide layer to remove a portion of the undoped oxide layer; depositing a first deep trench isolation (DTI) gap-fill layer on a remaining portion of the undoped oxide layer, and performing a second etch-back process on the first DTI gap-fill layer; depositing a second DTI gap-fill layer to seal the deep trench isolation, and forming a planarized second DTI gap-fill layer by a planarization process; and depositing a second undoped layer on the planarized second DTI gap-fill layer.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.