Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5 difference in width) but substantially the same height (e.g., less than 5 nm difference in height). A given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. According to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. Using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.

Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.

A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.

The present invention relates to an abrasive and a planarization method using the same, and more particularly, includes fumed silica. A BET specific surface area of the fumed silica is 200 m.sup.2/g to 450 m.sup.2/g, a shape of aggregates dispersed in the abrasive has an elongated shape or a round shape, and a ratio of the round shape of the aggregates is 50% to 90%.

A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

Trench isolation connectors are disclosed herein for stacked semiconductor structures, and particularly, for stacked semiconductor structures having high voltage devices. An exemplary stacked device arrangement includes a first device substrate having a first device and a second device substrate having a second device. An isolation structure disposed in the second device substrate surrounds the second device. The isolation structure extends through the second device substrate from a first surface of the second device substrate to a second surface of the second device substrate. A conductive connector is disposed in the isolation structure. The conductive connector is connected to the second device and the first device. The conductive connector extends from the first surface of the second device substrate to the second surface of the second device substrate. The first device and the second device may be a first high voltage device and a second high voltage device, respectively.

A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

A semiconductor device and method of forming the semiconductor device are disclosed. The method includes forming first and second conductive structures on a semiconductor substrate, forming one or more dielectric layers between the first and second conductive structures, covering the one or more dielectric layers with a first masking layer, forming a first opening in the first masking layer, depositing a conductive material in the first opening to form a field plate structure, and electrically connecting the field plate structure to another conductor.