A manufacturing method for a semiconductor device includes: obtaining a pre-processed semiconductor structure, wherein the pre-processed semiconductor structure comprises a metal layer (103) having a first exposed surface (1032), and the first exposed surface (1032) of the metal layer has a protrusion portion (1031); arranging a protective layer (104) on the first exposed surface (1032) of the metal layer, wherein the protective layer (104) at least covers part of the metal layer (103) that excludes the protrusion portion (1031); removing the protrusion portion (1031) to form on the metal layer (103) a second exposed surface (1033) of the metal layer (103); and forming a dielectric layer (105) on an area where the first exposed surface (1032) is located, wherein the dielectric layer (105) completely covers the area where the first exposed surface (1032) is located.

A display device includes a circuit substrate, light-emitting diodes, a bank structure, and light-transmission structures. The circuit substrate includes first sub-pixel areas, wherein each first sub-pixel area includes a placement area and a repair area. At least one corresponding light-emitting diode is disposed on at least one of the placement area and the repair area of each first sub-pixel area. The bank structure is located above the circuit substrate and has second sub-pixel areas. The first sub-pixel areas are overlapped with the second sub-pixel areas respectively. Each second sub-pixel area includes a preset opening and a repair opening. The preset openings are overlapped with the placement areas, and the repair openings are overlapped with the repair areas. The light-transmission structures are disposed in the second sub-pixel areas. Each light-transmission structure is disposed in one corresponding preset opening or in one corresponding repair opening.

An electronic device manufacturing system including a substrate-holder configured to secure a substrate during processing and a controller, operatively coupled to the substrate-holder. The controller is configured to apply, to an electrode of the substrate-holder, a first voltage. The controller is further configured to determine a first impedance value between the substrate-holder and the substrate. The controller is further configured to determine a delta value between the first impedance value and a predetermined second impedance value, and determine whether the delta value satisfies a threshold criterion. Responsive to the delta value failing to satisfy the threshold criterion, the controller is further configured to apply a second voltage to the substrate, wherein the second voltage is greater than the first voltage.

Methods and systems for improved simulation of thermal characterization and thermal modeling of devices, such as smart phones, are described. In one embodiment, a method can characterize center, edge, and corner thermal decay behavior at different locations on a simulated IC. For each location, near and far field thermal effects are captured at the same time. A simulation system can generate a steady state thermal decay curve for each selected location that shows how the temperature changes with distance to a heat source. The system can then use a set of location dependent thermal decay curves to compute, based on an inputted power profile for the IC, a steady state thermal profile of the IC.

A fabricating method for a test element group is provided. The fabricating method for a test element group includes fabricating test areas generated in a scribe lane area, wherein fabricating of the test areas includes forming a plurality of fins protruding in a first direction on a substrate, covering at least some of the plurality of fins with a masking material, and performing selective epitaxial growth by injecting a gas onto the plurality of fins. The gas is not injected onto the at least some of the plurality of fins that are covered with the masking material, such that the epitaxial growth does not occur on the fins covered with the masking material.

There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.

The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

A method of operating an electronic device for detecting a defect due to a particle in an equipment generated during a bonding process of a semiconductor chip is disclosed. For example, the method may include obtaining, by the electronic device, profile data including operation information of the equipment from the equipment during the bonding process. Additionally, the method may include calculating, by the electronic device, characteristic data of bonded chips (e.g., from the bonding process) by pre-processing the profile data. Subsequently, after the bonding process is completed, the method may include selecting, by the electronic device, a coordinate of a defective chip on a substrate as a defect coordinate by comparing result data of a reference chip and peripheral chips based on the characteristic data. In some embodiments, the result data may include respective height value information of the bonded chips.

The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.