A method of processing a wafer includes forming a bonded wafer assembly by bonding one of opposite surfaces of a first wafer to a second wafer, the first wafer having a device region and an outer circumferential excessive region, applying a laser beam to the first wafer while positioning a focused spot of the laser beam radially inwardly from the outer circumferential edge of the first wafer, on an inclined plane that is progressively closer to the one of the opposite surfaces of the first wafer toward the outer circumferential edge, thereby forming a separation layer shaped as a side surface of a truncated cone, grinding the first wafer from the other one of the opposite surfaces thereof to thin down the first wafer to a predetermined thickness, and detecting whether or not the outer circumferential excessive region has been removed from the first wafer.

The manufacturing historical data of each lot is collected during each manufacturing step of a manufacturing process for providing a manufacturing data set which is divided into a training data set and a testing data set. A preliminary random forest prediction model is built based on the characteristic values and an initial label of each piece of manufacturing historical data in the training data set. The preliminary random forest prediction model is then evaluated using each piece of manufacturing historical data in the testing data set for building an optimized random forest prediction model. The estimated start/end time of each manufacturing step in the manufacturing process may be acquired by inputting new data into the optimized random forest prediction model. The cycle time and turn rate of the manufacturing process may thus be optimized.

A method for detecting impurities on a surface of a silicon wafer for manufacturing semiconductors, the impurities not being able to be detected by a conventional inspection method, a method for manufacturing the silicon wafer for manufacturing semiconductors having the impurities removed from the surface thereof, and a method for screening wafers for manufacturing semiconductors. This method for detecting impurities on a surface of a wafer for manufacturing semiconductors includes: a step for coating the surface of the wafer with a film-forming composition, and performing baking to form a film; and then a step for detecting impurities by means of a wafer inspection tool.

Provided is a semiconductor package, including a first semiconductor chip, and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes a test pattern, and wherein a frequency based on stress being exerted on the first semiconductor chip is measured based on the test pattern.

A system acquires a temperature TB of a temperature-controlling medium before a temperature change during execution of a plurality of processes n (n is identifier of process and is natural number that is greater than one) in each of which heat is input to a substrate placed on a placement surface of a stage, wherein the placement surface on which the substrate is placed is formed on the stage, a flow path through which the temperature-controlling medium having an adjusted temperature flows is formed in the stage, and a discharge port via which heat transfer gas is discharged toward the placement surface is formed in the stage; and for each of the processes n, a pressure P.sub.n of heat transfer gas supplied to the discharge port and a temperature TW.sub.n of the substrate. The system also adjusts a pressure of heat transfer gas so as to control temperature of substrate.

A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

A substrate processing system includes a processing chamber, a substrate support, a heat source, a gas delivery system and a controller. The substrate support is disposed in the processing chamber and supports a substrate. The heat source heats the substrate. The gas delivery system supplies a process gas to the processing chamber. The controller controls the gas delivery system and the heat source to iteratively perform an isotropic atomic layer etch process including: during an iteration of the isotropic atomic layer etch process, performing pretreatment, atomistic adsorption, and pulsed thermal annealing; during the atomistic adsorption, exposing a surface of the substrate to the process gas including a halogen species that is selectively adsorbed onto an exposed material of the substrate to form a modified material; and during the pulsed thermal annealing, pulsing the heat source multiple times within a predetermined period to expose and remove the modified material.

An apparatus includes a processing chamber, a substrate support in the processing chamber, a plasma source coupled to the processing chamber, and a plurality of heating devices arranged on the processing chamber. Each heating device is configured to emit laser beam on a substrate positioned on the substrate support to heat the substrate.

A control device for controlling a state quantity in a substrate processing apparatus performing processing on a substrate, the control device includes: a feedback controller configured to apply a control signal to a control target, based on a deviation between a target value of the state quantity and a detected value from a detector; and a correction value calculator configured to acquire a deviation e.sub.j between the target value and the detected value in j-th substrate processing (where j is an integer of 1 or greater) and calculate a correction value to be added to the control signal from the feedback controller during (j+1)-th substrate processing, so that a deviation e.sub.j+1 between the target value and the detected value in the (j+1)-th substrate processing becomes smaller than the deviation e.sub.j.

A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.