A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Methods of making high-pixel-density LED structures are described. The methods may include forming a backplane substrate and a LED substrate. The backplane substrate and the LED substrate may be bonded together, and the bonded substrates may include an array of LED pixels. Each of the LED pixels may include a group of isolated subpixels. A quantum dot layer may be formed on at least one of the isolated subpixels in each of the LED pixels. The methods may further include repairing at least one defective LED pixel by forming a replacement quantum dot layer on a quantum-dot-layer-free subpixel in the defective LED pixel. The methods may also include forming a UV barrier layer on the array of LED pixels after the repairing of the at least one defective LED pixel.

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

A system includes a vacuum chamber having a wafer chuck therein and side windows slanted relative to the wafer chuck. A wafer stage is positioned below the wafer chuck and configured to rotate the wafer chuck and move the wafer chuck vertically. Illumination optics, including an illumination corrector lens, are configured to receive light and direct the light through an illumination vacuum window of the side windows to an optical spot on the wafer. Collection optics, including a collection corrector lens, are configured to receive the light from the optical spot through a collection vacuum window of the side windows and direct the light to a detector. A transfer module is configured to move the illumination optics and the collection optics parallel to the illumination vacuum window and the collection vacuum window respectively. The illumination corrector lens and the collection corrector lens are configured to reduce chromatic aberration.

A method of creating a correlation relational formula for determining a polishing condition, the method including polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane polishing amount distribution information on the semiconductor wafers in polishing under the plurality of polishing conditions; polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane temperature distribution information during semiconductor wafer polishing in polishing under the plurality of polishing conditions, or creating in-plane temperature distribution information during semiconductor wafer polishing under polishing conditions including a plurality of polishing parameters by heat transfer analysis, and correlating relational formulas between a semiconductor wafer in-plane temperature distribution parameter and a plurality of polishing parameters.