A wafer, electronic component and method are disclosed. In one example, the wafer comprises an array of a plurality of electronic components. The separation frame separating neighboured electronic components, wherein the separation frame comprises a laser penetration affecting structure configured for locally affecting laser penetration when subjecting the separation frame to laser processing during stealth dicing.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

There is provided a semiconductor package having improved reliability. The semiconductor package comprising, a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate, an interposer substrate on the first package, a second package including a second package substrate on the interposer substrate, and the second package substrate including a first surface and a second surface opposite to each other, a plurality of solder balls attached onto the first surface of the second package substrate, and the plurality of solder balls connecting the second package substrate and the interposer substrate, and a second semiconductor chip mounted on the second surface of the second package substrate, and a second capacitor between the interposer substrate and the second package substrate, the second capacitor mounted on the interposer substrate and electrically connected to the second semiconductor chip.

The present invention provides an electronic or electrical device or component thereof comprising a cross-linked polymeric coating on a surface of the electronic or electrical device or component thereof; wherein the cross-linked polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising a monomer compound and a crosslinking reagent for a period of time sufficient to allow formation of the cross-linked polymeric coating on a surface thereof.

An electronic chip includes a crack detection device formed inside and on top of a substrate or on top of the substrate. The device includes a conductive path made of an alternation of lower and upper conductive strips, where each lower strip includes first and second conductive vias in contact with the lower strip, third and fourth conductive vias in contact with respectively an upper strip and another upper strip, and first and second conductive tracks respectively connecting the first and third vias and the second and fourth vias. The first and second vias are located vertically in line respectively with a first end and a second end of the lower strip, and the third and fourth vias are located vertically in line respectively with one end of the upper strip and of the other upper strip.

A semiconductor package is provided. The semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip of the plurality of first semiconductor chips, and a molding structure surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip, the channel has a shape extending from a center of the dummy chip to at least any one point located at an edge of the dummy chip, in a horizontal direction in a top view, and the molding structure fills the channel.

Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.