An embodiment of the disclosure provides an electronic assembly including a stacked structure, a first integrated circuit, a first passive component, and a first electrode. The stacked structure comprises a plurality of insulating layers and a plurality of conductive layers. The first passive component is disposed between the stacked structure and the first integrated circuit. The first electrode is disposed between the stacked structure and the first passive component. The first passive component is electrically connected to the stacked structure through the first electrode.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A low parasitic inductance power module having staggered, interleaving busbars, including: at least one base extending a long a length direction, the base having at least one current input busbar and at least one current output busbar, the current input busbar and the current out busbar being formed with a plurality of interdigitated contact terminals, respectively; a first unit comprising a first circuit base portion disposed on the base along the width direction, on the first circuit base portion being disposed a plurality of first power devices; and a second unit, whereby when current flows through the units and the individual interdigitated contact terminals, individual inductances produced thereby are cancelled with each other, whereby overall parasitic inductance of the power module is reduced.

An electrical device including a first cylindrical capacitor, a first terminal electrically coupled to one end of the first capacitor, a first electrical line electrically coupled to the first terminal and a first annular conductive end shield formed over the first terminal and being electrically coupled to the first terminal and the one end of the first capacitor, where the first end shield has a greater diameter than the diameter of the first capacitor. The device also includes a second cylindrical capacitor, a second terminal electrically coupled to one end of the second capacitor, a second electrical line electrically coupled to the second terminal and a second annular conductive end shield formed over the second terminal and being electrically coupled to the second terminal and the one end of the second capacitor, where the second end shield has a greater diameter than the diameter of the second capacitor.

An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a magnetic ring is embedded in the substrate. In an embodiment, a loop is around the magnetic ring. In an embodiment, the loop is conductive and comprises a first via through the substrate, a second via through the substrate, and a trace over a surface of the substrate, where the trace electrically couples the first via to the second via.

An apparatus and method for manufacturing a power module is provided. The power module includes: a circuit board having a metal pattern formed thereon; a terminal coupled to the circuit board and electrically connected to at least a portion of the metal pattern; a power device chip bonded to the circuit board and electrically connected to at least a portion of the metal pattern and the terminal; and a molding part covering the power device chip and the circuit board. The circuit board includes: a base part comprising an insulating material; a pattern layer disposed on at least one of an upper surface and a lower surface of the base part and providing the metal pattern; and a thin film resistor having a predetermined circuit pattern connecting the metal patterns disposed on the base part to each other.

An assembly includes a passive component embodied as a shunt resistor, and a first substrate including a first conductor track and a second conductor track, with the first conductor track being electrically conductively connected to the second conductor track by way of the passive component. The first substrate includes a cavity or an opening into which the passive component protrudes. A second substrate is electrically conductively connected to the first substrate by way of the passive component and includes a dielectric material layer. A heat sink is arranged on a side of the second substrate facing away from the first substrate and is connected to the passive component in an electrically insulating and thermally conductive manner by way of the dielectric material layer of the second substrate. The passive component is arranged on a side of the second substrate facing toward the first substrate.

A semiconductor module includes a first logic chip including a first surface and a second surface parallel to a first direction and a second direction, a first semiconductor chip including a third surface and a fourth surface, arranged on the second surface, and connected to the first logic chip, and a semiconductor cube arranged on the fourth surface, the semiconductor cube including a plurality of second semiconductor chips stacked in the first direction. The second semiconductor chip includes a first inductor arranged in a third direction perpendicular to the first and second directions, and the first semiconductor chip includes a plurality of routers and a second inductor arranged parallel to the fourth surface. The plurality of circuits in the first logic chip and the plurality of circuits in the first semiconductor chip are connected using the plurality of routers, and enable contactless communication with the plurality of second semiconductor chips.

A semiconductor structure is provided. The semiconductor structure includes a substrate and a deep trench capacitor (DTC) region formed in the substrate. The DTC region includes a plurality of DTC units, and each DTC unit includes: a trench extending downwardly from a top surface of the substrate; a first conductive layer disposed in the trench; a second conductive layer disposed in the trench; and a dielectric layer sandwiched by the first conductive layer and the second conductive layer. Each DTC unit is elongated, and a first group of the plurality of DTC units extend horizontally in a first direction, whereas a second group of the plurality of the DTC units extend horizontally in a second direction.