A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

Methods, devices, and systems for driving optical modulators. An example integrated circuit includes a driver including: a first circuit having a first switch coupled between a first input and a first output and a second circuit having a second switch coupled between a second input and a second output. Each of the first and second switches is configured to receive a control signal adjustable to control a corresponding signal path with a corresponding input electronic signal. The first and second circuits are configured to control a rising edge and a falling edge of an output electronic signal at an output of the driver that is based on a first output electronic signal at the first output and a second output electronic signal at the second output. The output of the driver is electrically coupled to the optical modulator to provide the output electronic signal to modulate an optical signal.

Example embodiments are directed to a semiconductor package for improving Signal Integrity (SI) characteristics. The semiconductor package includes a package substrate, a mediate substrate arranged on the package substrate and including an active layer and a wiring layer, and at least two semiconductor devices on the mediate substrate. The wiring layer includes path wirings configured to connect the at least two semiconductor devices to each other. The path wirings include n paths (n is an integer that is 2 or more), and the active layer includes a selection circuit configured to select one of the n paths.

According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.

Methods, devices, and systems for driving optical modulators. An example integrated circuit includes a driver including a first circuit having a first switch coupled between a first input and a first output and a second circuit having a second switch coupled between a second input and a second output. Each of the first and second switches is configured to receive a control signal adjustable to control a corresponding signal path with a corresponding input electronic signal. The first and second circuits are configured to control a rising edge and a falling edge of an output electronic signal at an output of the driver that is based on a first output electronic signal at the first output and a second output electronic signal at the second output. The output of the driver is electrically coupled to the optical modulator to provide the output electronic signal to modulate an optical signal.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.

A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes a central region and an edge region outside the central region; one or more electronic components disposed within the central region; and a plurality of through-chiplet vias extending through the chiplet. The plurality of through-chiplet vias are disposed in the edge region. The device may further include a coil including a plurality of turns formed in at least two chiplets of the plurality of chiplets. Each turn includes at least two through-chiplet vias of at least one chiplet of the plurality of chiplets. The through-chiplet vias of the plurality of through-chiplet vias of the at least two turns of the plurality of turns of the coil are formed in a common plane perpendicular to main surfaces of the plurality of chiplets.

A device comprising a substrate, a first integrated device coupled to a first surface of the substrate, a second integrated device coupled to the first surface of the substrate, a first passive device coupled to a second surface of the substrate and a second passive device coupled to the second surface of the substrate. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects are configured to operate as an inductor, where the first plurality of interconnects include a via interconnect.

Provided is a semiconductor package including a package substrate, a stacked structure mounted on the package substrate, and a heat dissipation structure mounted on the stacked structure, wherein the stacked structure includes a lower die, a passive device chip, a second upper die arranged apart from the passive device chip on the lower die, and a first upper die mounted on the passive device chip, and wherein the lower die includes a voltage control chip, the passive device chip includes a capacitor, and the package substrate includes an inductor.