The Digital Time Processing over Time Sensitive Networks (DTP TSN) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks recovered from PTP messages and/or compatible with them data receiver clocks for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages, wherein such distribution of the master time includes filtering out phase noise of a timing referencing signals communicated by PTP messages in order to produce accurate timing implementing signals such as the slave clock, local slave time and local master time.

An article management device includes a processing circuit. The processing circuit is configured to repeatedly acquire, from a wireless tag attached to an article where the wireless tag is capable of measuring an environmental physical quantity related to the article, identification information that identifies the wireless tag and the environmental physical quantity; monitor an amount of time that the environmental physical quantity exceeds a first threshold value in response to the environmental physical quantity exceeding the first threshold value; and record the amount of time in association with the identification information.

An article management device includes a processing circuit. The processing circuit is configured to repeatedly acquire, from a wireless tag attached to an article where the wireless tag is capable of measuring an environmental physical quantity related to the article, identification information that identifies the wireless tag and the environmental physical quantity; monitor an amount of time that the environmental physical quantity exceeds a first threshold value in response to the environmental physical quantity exceeding the first threshold value; and record the amount of time in association with the identification information.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

Time-to-digital converter arrangement having a first and a second time-to-digital converters. The first one is configured to determine the existence or nonexistence of an event in a recurring first measurement window. The second one is configured to determine the existence or nonexistence of the event in a recurring second measurement window. A temporal relation of the second measurement window with respect to detecting the event is time-shifted by a first offset compared to a temporal relation of the first measurement window with respect to detecting the event.

A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

Provided is a chronograph for including an electronic computer, power supply means, a non-volatile memory and a volatile memory; control means operatively connected to said computer; a display operatively connected to said computer; the electronic computer including electronic means, including a programme defined by a machine-type language for memorising a set date on said non-volatile memory which cannot be changed after the first setting, the electronic computer further including means for calculating the elapsed time between the set date and the current date.

Provided is a chronograph for including an electronic computer, power supply means, a non-volatile memory and a volatile memory; control means operatively connected to said computer; a display operatively connected to said computer; the electronic computer including electronic means, including a programme defined by a machine-type language for memorising a set date on said non-volatile memory which cannot be changed after the first setting, the electronic computer further including means for calculating the elapsed time between the set date and the current date.

Various embodiments of the present technology may provide methods and apparatus for repetitive histogramming. The apparatus may provide a limited number of physical bins to perform multiple histograms on a total number of virtual bins. The apparatus may provide a single physical bin that is used to sweep over the total number of virtual bins.