A method of communication between an Ethernet Media Access Controller (MAC) and a physical interface (PHY) is disclosed. The method includes establishing communication between the MAC and the PHY via a first serial link in accordance with a Serializer Deserializer (SERDES) protocol. In a data transfer mode, data is transferred along the first serial link. Idle frames are transferred within an idle time gap along the link in an idle mode. The PHY is managed by encoding Management Data Input/Output (MDIO) information in one or more MDIO frames, and transferring the one or more MDIO frames within the idle time gap along the first serial link.

A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D) on the basis of the values of the sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D) and the delays introduced by the delay elements (21, 22, 23).

A method for identifying a set of interpolation point data points from training data for a sparse Gaussian process model, encompassing the following tasks: successively selecting training data points from the set of training data for acceptance into or exclusion from a set of interpolation point data points in accordance with a selection criterion; and terminating selection when a termination criterion exists; the selection criterion depending on a divergence between a target value of the selected training data point and a function value, at the selected training data point, of the Gaussian process model based on the respectively current set of interpolation point data points.

One disclosed method includes generating a rule set by an application running on a primary processor. The rule set specifies how the application handles events. The rule set is sent from the primary processor to a secondary processor and the primary processor is placed in sleep mode. The secondary processor may then handle at least one event corresponding to the application by executing the rule set while the primary processor is in sleep mode. In one embodiment, handling the event may include substituting for the application by the secondary processor by executing the rule set, and controlling a peripheral hardware device that is peripheral to the primary processor according to the rule set. Handling an event may also include waking the primary processor from sleep mode by the secondary processor and passing control back to the primary processor.

An on-chip sensor hub fabricated on a chip with a main processor of a mobile device, and the mobile device, and a method for multi-sensor management on the mobile device. An on-chip sensor hub includes a co-processor and uses an inter-process communication interface. The co-processor and main processor of the mobile device are fabricated on the same chip and communicate with each other via the inter-process communication interface. The co-processor controls a plurality of sensors in the mobile device in accordance with requests issued from the main processor. The co-processor further collects and manages sensor data from the sensors to be processed by the main processor.

An improved management of an electrical power transmission network is obtained by providing at each of the subscriber premises a load control device which includes a power correction system for applying a capacitive load and/or a switched reactor for voltage correction across the input voltage and a sensing system defined by a pair of meters one at the supply and the second downstream of the voltage correction for detecting variations in power factor. A control system operates to control the power correction system in response to variations detected by the sensing system and to communicate between the load control device and the network control system so as to provide a bi-directional interactive system.

Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

A storage device includes an extension chip and an energy-efficiency control circuit. The extension chip includes an input interface electrically coupled to a motherboard and an output interface. The energy-efficiency control circuit is electrically coupled between the motherboard and the extension chip. The energy-efficiency control circuit includes an interface module, a control module, and a switch module. The interface module is electrically coupled to the input interface of the extension chip, and configured to receive a control signal from the motherboard. The control module is electrically coupled to the interface module, to configured receive the control signal, and to output an output signal according to the control signal received. The switch module is electrically coupled to the control module and a first power supply terminal, to receive the output signal, and to output a voltage of the first power supply terminal to a storage unit.

In the context of computer systems, the present invention broadly contemplates the ability to dynamically adjust the voltage and frequency of DRAM memory modules that are dual-voltage tolerant based on system performance. The invention allows a computer system to dynamically scale the memory voltage between a lower and a higher voltage, thereby allowing the system to save power when the system is idle or in low usage, but also allowing the system to realize the full memory performance when running more intensive applications.

An image processing apparatus includes a chipset unit which processes data; a connector which includes a plurality of terminals, and is configured to connect with a cable so that the chipset unit can transmit and receive a signal to and from an external device; a switching unit which supplies power to the external device through a first terminal of the connector, and selectively controls a switching operation regarding whether or not to supply power to the first terminal on the basis of a signal state of a second terminal of the connector when the cable is connected to the connector. A control method of the image processing apparatus is also disclosed.