An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.

The present disclosure provides compositions and methods for selectively killing cancer cells, wherein the composition comprises a compound of Formula (I). The selective killing of cancer cells occurs with an improved potency and safety profile compared to similar compounds. In particular, the compositions and methods of the invention show reduced platelet toxicity and retained or improved toxicity in cancer cells.

The present disclosure provides compositions and methods for selectively killing cancer cells, wherein the composition comprises a compound of Formula (I). The selective killing of cancer cells occurs with an improved potency and safety profile compared to similar compounds. In particular, the compositions and methods of the invention show reduced platelet toxicity and retained or improved toxicity in cancer cells.

Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

A circuit for fast matrix-vector multiplication and a method for constructing that circuit are provided, comprising processing a matrix to obtain a pair matrix, which is then used to construct a circuit.

A processor includes a linear approximator and a front end including circuitry to assign linear approximation of a nonlinear function to a linear approximator. The linear approximator includes circuitry to divide a range of values for the linear approximation into a defined number of segments, perform linear approximation for each segment, move borders between the segments to reduce discontinuity moving along segments of variable length, repeat linear approximation for each segment until convergence, and return values for the linear approximation.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.