Disclosed herein is an apparatus and method for managing an Artificial Intelligence (AI) operation based on an analog device. The method may include setting a first layer list to use an analog operation unit and analog memory based on a performance improvement effect obtained by using the analog operation unit, among layers constituting an AI model, setting a second layer list to use a digital operation unit and the analog memory based on a digital memory saving effect obtained by using the analog memory, among remaining layers excluding the first layer list from the layers constituting the AI model, and setting remaining layers excluding the first layer list and the second layer list from the layers constituting the AI model as a third layer list to use digital memory and the digital operation unit.

Disclosed herein is an apparatus and method for managing an Artificial Intelligence (AI) operation based on an analog device. The method may include setting a first layer list to use an analog operation unit and analog memory based on a performance improvement effect obtained by using the analog operation unit, among layers constituting an AI model, setting a second layer list to use a digital operation unit and the analog memory based on a digital memory saving effect obtained by using the analog memory, among remaining layers excluding the first layer list from the layers constituting the AI model, and setting remaining layers excluding the first layer list and the second layer list from the layers constituting the AI model as a third layer list to use digital memory and the digital operation unit.

A memory device includes a memory cell array including ferroelectric memory cells, respectively disposed at intersections of wordlines and bitlines, and an analog-to-digital converter that is selectively connected to the bitlines and that outputs a digital value corresponding to charges applied through a bitline of the bitlines. The charges correspond to a piece of multi-bit data having digits stored in a portion of the ferroelectric memory cells that are connected to the bitline.

A memory device includes a memory cell array including ferroelectric memory cells, respectively disposed at intersections of wordlines and bitlines, and an analog-to-digital converter that is selectively connected to the bitlines and that outputs a digital value corresponding to charges applied through a bitline of the bitlines. The charges correspond to a piece of multi-bit data having digits stored in a portion of the ferroelectric memory cells that are connected to the bitline.

An electronic circuit is provided. The electronic circuit includes a plurality of digital-to-analog converters (DACs) configured to generate a plurality of analog input signals. The electronic circuit includes a computation matrix coupled to the plurality of DACs and configured to receive the plurality of analog input signals from the plurality of DACs. The computation matrix comprises a plurality of computation nodes. Each computation node comprises: a bias circuit configured to generate a positive bias current and a negative bias current based on an analog input signal among the plurality of analog input signals, and a computation circuit configured to generate a computation result current based on the positive bias current, the negative bias current, and a digital weight signal. An electronic device and a method are also provided.

An electronic circuit is provided. The electronic circuit includes a plurality of digital-to-analog converters (DACs) configured to generate a plurality of analog input signals. The electronic circuit includes a computation matrix coupled to the plurality of DACs and configured to receive the plurality of analog input signals from the plurality of DACs. The computation matrix comprises a plurality of computation nodes. Each computation node comprises: a bias circuit configured to generate a positive bias current and a negative bias current based on an analog input signal among the plurality of analog input signals, and a computation circuit configured to generate a computation result current based on the positive bias current, the negative bias current, and a digital weight signal. An electronic device and a method are also provided.

Certain aspects of the present disclosure provide techniques for processing machine learning model data with a machine learning task accelerator, including: configuring one or more signal processing units (SPUs) of the machine learning task accelerator to process a machine learning model; providing model input data to the one or more configured SPUs; processing the model input data with the machine learning model using the one or more configured SPUs; and receiving output data from the one or more configured SPUs.

The present disclosure provides methods and systems for using a hybrid architecture of classical and non-classical (e.g., quantum) computing to compute the quantum mechanical energy and/or electronic structure of a chemical system, as well as to identify stable conformations of a chemical system (e.g., a molecule) and/or to perform an ab initio molecular dynamics calculation or simulation on the chemical system.

The present disclosure provides methods and systems for using a hybrid architecture of classical and non-classical (e.g., quantum) computing to compute the quantum mechanical energy and/or electronic structure of a chemical system, as well as to identify stable conformations of a chemical system (e.g., a molecule) and/or to perform an ab initio molecular dynamics calculation or simulation on the chemical system.