In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2.sup.m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2.sup.m different analog voltages to an associated row in the array.

Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2.sup.m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2.sup.m different analog voltages to an associated row in the array.

A hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element (PE) for machine learning (ML) applications is disclosed. The hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add PE for ML applications involves using Fin Field-Effect Transistors (FinFETs), which provide excellent sub-threshold operation, thereby reducing power requirements, and use variation minimization strategies to improve the overall accuracy. In this way, hybrid analog-digital mixed-mode matrix multiply-add calculations are efficient, low power, and accurate, with the processing element itself in a relatively small surface area.

A hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element (PE) for machine learning (ML) applications is disclosed. The hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add PE for ML applications involves using Fin Field-Effect Transistors (FinFETs), which provide excellent sub-threshold operation, thereby reducing power requirements, and use variation minimization strategies to improve the overall accuracy. In this way, hybrid analog-digital mixed-mode matrix multiply-add calculations are efficient, low power, and accurate, with the processing element itself in a relatively small surface area.

An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

Various embodiments are described that relate to random number generation. When a desire arises for a random number a circuit can be completed with a reverse biased semiconductor junction element. When the circuit is completed an analog voltage spike can be produced that is random due to properties of the reverse biased semiconductor-junction element. This analog voltage spike can be converted into a digital value that serves as the random number. The digital value can be outputted and used as the random number.

A voltage controlled impedance synthesizer providing stepwise variable impedance values according to a prescribed function of the control voltage, said synthesizer comprises of one or more two-terminal impedance modules connected in series, in each impedance module one or more essentially identical two-terminal impedance elements connected in series, a corresponding number of switches to short out by selection none to all of the impedance elements in the impedance module, and said switches being controlled by the control voltage through analog-to-digital conversion and digital processing means. The values of the impedance elements between the impedance modules in ratios being uniquely defined according to the numbers of impedance elements in the impedance modules, the voltage controlled impedance synthesizer is controlled to provide monotonic and stepwise variable impedance values. Further, through the use of the voltage controlled impedance synthesizer, other electrical parameters such as current and power can be controlled according to any prescribed functions.

A voltage controlled impedance synthesizer providing stepwise variable impedance values according to a prescribed function of the control voltage, said synthesizer comprises of one or more two-terminal impedance modules connected in series, in each impedance module one or more essentially identical two-terminal impedance elements connected in series, a corresponding number of switches to short out by selection none to all of the impedance elements in the impedance module, and said switches being controlled by the control voltage through analog-to-digital conversion and digital processing means. The values of the impedance elements between the impedance modules in ratios being uniquely defined according to the numbers of impedance elements in the impedance modules, the voltage controlled impedance synthesizer is controlled to provide monotonic and stepwise variable impedance values. Further, through the use of the voltage controlled impedance synthesizer, other electrical parameters such as current and power can be controlled according to any prescribed functions.