Disclosed herein is a method of: placing between a cooling element and an opposing surface a slurry of: a dielectric powder containing barium titanate, a dispersant, a binder, and water; maintaining the cooling element at a temperature below the opposing surface to cause the formation of ice platelets perpendicular to the surface of the cooling element and having the powder between the platelets; subliming the ice platelets to create voids; sintering the powder to form the dielectric material; and filling the voids with the polymeric material. The process can produce a composite having: a sintered dielectric material of barium titanate and platelets of a polymeric material embedded in the dielectric material. Each of the platelets is perpendicular to a surface of the composite.

A manufacturing method for a magnetic head forms a leading shield having a top surface. The top surface of the leading shield includes first and second portions. The second portion is located farther from a medium facing surface than is the first portion, and recessed from the first portion. A first gap layer is then formed on the first portion. Then, a magnetic layer including an initial first side shield, an initial second side shield and a coupling section connecting them is formed using a mold. The mold is then removed. The coupling section is then removed by etching the magnetic layer. A second gap layer and a main pole are then formed in this order.

Structures, including a capacitor, and methods for forming the structures are provided. One such structure may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric. Other structures and methods are disclosed.

A capacitor includes a dielectric layer, a first conductive layer, a second conductive layer, first inner electrodes, second inner electrodes, a first external power electrode layer, a second external power electrode layer, a first outer electrode, and a second outer electrode. The first and second inner electrodes and first and second second outer electrodes are a conductive material. The dielectric layer has through-holes connecting with a first main surface and a second main surface. The first inner electrodes are in a first set of the through-holes and connected to the first conductive layer. The second inner electrodes are in a second set of the through-holes and connected to the second conductive layer. The first outer electrode is on the first external power electrode layer and some side-faces of the dielectric layer. The second outer electrode is on the second external power electrode layer and some side-faces of the dielectric layer.

A capacitor includes a dielectric layer, a first conductive layer, a second conductive layer, first inner electrodes, second inner electrodes, a first external power electrode layer, a second external power electrode layer, a first outer electrode, and a second outer electrode. The first and second inner electrodes and first and second second outer electrodes are a conductive material. The dielectric layer has through-holes connecting with a first main surface and a second main surface. The first inner electrodes are in a first set of the through-holes and connected to the first conductive layer. The second inner electrodes are in a second set of the through-holes and connected to the second conductive layer. The first outer electrode is on the first external power electrode layer and some side-faces of the dielectric layer. The second outer electrode is on the second external power electrode layer and some side-faces of the dielectric layer.

A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

A process of forming a cross-linked electronically active hydrophilic co-polymer is provided and includes the steps of: a. mixing an intrinsically electronically active material and at least one compound of formula (I) with water to form an intermediate mixture; b. adding at least one hydrophilic monomer, at least one hydrophobic monomer, and at least one cross-linker to the intermediate mixture to form a co-monomer mixture; and c. polymerising the co-monomer mixture. Formula (I) is defined as: ##STR00001##
where R.sup.1 and R.sup.2 are independently optionally substituted C.sub.1-C.sub.6 alkyl and X.sup.− is an anion.

A method for manufacturing a ceramic electronic component includes a ceramic chip element assembly production step of producing ceramic chip element assemblies, a jig preparation step of preparing a jig with chip storing portions including a bottom portion to support a ceramic chip element assembly from below and an open-top side wall portion, a ceramic chip element assembly storing step of storing the ceramic chip element assemblies in the chip storing portions in a one-to-one correspondence, a ceramic chip element assembly working step of working the ceramic chip element assemblies stored in the chip storing portions, and a ceramic chip element assembly removal step of removing the ceramic chip element assemblies from the chip storing portions.

Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.