Patent classifications
H01G4/00
Laminated ceramic chip component including nano thin film layer, manufacturing method therefor, and atomic layer vapor deposition apparatus therefor
The present disclosure discloses the laminated ceramic chimp component including an element part having a ceramic main body and an internal electrode placed in the ceramic main body; an external electrode part having a first external electrode and a second external electrode, the first and second external electrodes being provided with side electrodes covering both side surfaces of the ceramic main body, respectively, upper electrodes covering portions of both sides of an upper surface of the ceramic main body, respectively, and lower electrodes covering portions of both sides of a lower surface of the ceramic main body, respectively; and a nano thin film layer formed of electric insulation material and applied to a region including the upper electrodes, the method for manufacturing the same and the atomic layer deposition apparatus for the same.
Capacitor having multiple graphene structures
A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
MULTILAYER BODY PRODUCTION METHOD, CAPACITOR PRODUCTION METHOD, MULTILAYER BODY, CAPACITOR, ELECTRIC CIRCUIT, CIRCUIT BOARD, AND DEVICE
A multilayer body of the present disclosure includes a support, a bismuth-including layer, and an intermediate layer. The bismuth-including layer includes at least one selected from the group consisting of pure bismuth, a bismuth alloy, bismuth oxide, and a composite oxide including bismuth. The intermediate layer includes at least one selected from the group consisting of pure zinc, a zinc alloy, pure tin, a tin alloy, pure lead, and a lead alloy. Additionally, the intermediate layer is disposed between the bismuth-including layer and the support in a thickness direction of the bismuth-including layer.
High quality factor time delay filters using multi-layer fringe capacitors
A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.
High quality factor time delay filters using multi-layer fringe capacitors
A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.
METALLIZED SEMICONDUCTOR DIE AND MANUFACTURING METHOD
A semiconductor die and a method for manufacturing a semiconductor die are disclosed. In an embodiment a semiconductor die includes a base body having a semiconductor material and a surface with two contact areas having contact pads at which the semiconductor die is electrically contactable and two metal caps arranged directly at the contact pads.
PLASMA ELECTRIC PROPULSION DEVICE
The present disclosure provides a plasma electric propulsion device comprising a capacitive energy storage device as a power source for an engine configured to heat and/or ionize and/or accelerate a propellant due to action of an electric field and/or magnetic field. The energy storage device comprises: a first electrically conductive electrode, a second electrically conductive electrode; and at least one metadielectric layer located between the first and second conductive electrodes. The metadielectric layer comprises at least one organic compound with at least one electrically resistive substituent and at least one polarizable unit. The polarizable unit is selected from intramolecular and intermolecular polarizable units. The organic compound is selected from the list comprising compounds with rigid electro-polarizable organic units, composite organic polarizable compounds, composite electro-polarizable organic compounds, composite non-linear electro-polarizable compounds, Sharp polymers, Furuta co-polymers, para-Furuta polymers, YanLi polymers, and any combination thereof.
JUMPER CABLE WITH CAPACITIVE POWER ENHANCEMENT AND/OR OVERVOLTAGE PROTECTION
A hybrid jumper cable includes: a pair of power conductors; a pair of optical fibers; a jacket surrounding the pair of power conductors and the pair of optical fibers; a hybrid connector connected with the pair of power conductors and the pair of optical fibers; a capacitor electrically connected to each of the pair of power conductors; and a conduit attached to the hybrid connector, the capacitor residing in the conduit.
Semiconductor Devices and Methods of Forming the Same
A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
HIGH QUALITY FACTOR TIME DELAY FILTERS USING MULTI-LAYER FRINGE CAPACITORS
A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.