Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a circuit substrate, a semiconductor chip mounted on the circuit substrate, and a thermal radiation film covering the semiconductor chip on the circuit substrate. The semiconductor chip includes first lateral surfaces opposite to each other in a first direction and second lateral surfaces opposite to each other in a second direction that intersects the first direction. A first width of the first lateral surface is less than a second width of the second lateral surface. The thermal radiation film covers a top surface of the semiconductor chip and entirely surrounds the first and second lateral surfaces of the semiconductor chip. The thermal radiation film has slits directed toward the first lateral surfaces from ends of the thermal radiation film.

The present invention relates to a power module and a method for manufacturing same, in which an insulating spacer is disposed between two upper and lower substrates to thus efficiently dissipate the heat generated from a semiconductor chip mounted between the substrates, and prevent bending deformation due to heat. In addition, since the spacer made of an insulating material is integrated with the substrates by brazing bonding, the bonding strength is improved, thereby maintaining strong bonding even against vibration, etc.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.

A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

There is provided a method of plating comprising: a process of bringing a sealing portion of a seal provided to prevent a contact of a substrate holder that holds a substrate from coming into contact with a plating solution, into contact with pure water; and a process of detecting a leak of the seal, based on presence or absence of a short circuit of a leak detection electrode placed inside of the substrate holder after the sealing portion is brought into contact with the pure water and before the substrate is brought into contact with a chemical solution.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

An electronic element soldering method includes providing a substrate, wherein the substrate has a to-be-soldered position, placing an electronic device including an electronic element, a heating element, and a parallel-connected circuit on the to-be-soldered position of the substrate, adding a solder between the electronic element of the electronic device and the to-be-soldered position of the substrate, applying a heating current into the parallel-connected circuit of the electronic device to allow the heating element of the parallel-connected circuit to generate a thermal energy for melting the solder, thereby securing the electronic element on the to-be-soldered position of the substrate via the solder that is melted, applying a breaking current that is larger than the heating current into the parallel-connected circuit to allow an open to occur in a parallel branch corresponding to the heating element of the parallel-connected circuit, and stopping the breaking current.

A semiconductor element arrangement structure is provided. The semiconductor element arrangement structure includes a carrier substrate, first and second adhesive layers respectively disposed on the carrier substrate and separated from each other, and first and second semiconductor elements disposed on the first and second adhesive layers, respectively. The first semiconductor element has first and second electrodes on the same side of the first semiconductor element, and the second semiconductor element has third and fourth electrodes on the same side of the second semiconductor element. The first adhesive layer is in direct contact with the first and second electrodes, and the second adhesive layer is in direct contact with the third and fourth electrodes. The first adhesive layer has a first width between the first and second electrodes and has a second width not between the first and second electrodes that is less than the first width.

A semiconductor device includes a semiconductor stack, a protective layer on the semiconductor stack, an electrode on the semiconductor stack and electrically connected to the semiconductor stack, and a conductive bump on the electrode. The thickness of the conductive bump is measured from the topmost point of the conductive bump to the uppermost surface of the protective layer. The ratio of the thickness of the conductive bump to the maximum width of the conductive bump is between 0.1 and 0.4.