An image-capturing device includes an image sensor. The image sensor includes an upper layer pixel group and a lower layer pixel group that receives the light fluxes from the subject that have passed through each pixel in the upper layer pixel group. The lower layer pixel group includes fourth, fifth and sixth pixels having fourth, fifth and sixth spectral sensitivities, respectively, that are complementary to first, second, and third spectral sensitivities, respectively, of the upper layer pixel group, being arranged in a two-dimensional pattern. Positions of first, second and third pixels in the upper layer pixel group and positions of the fourth, fifth and sixth pixels in the lower layer pixel group are determined such that the fourth, fifth and sixth pixels receive light fluxes that pass through the first, second and third pixels, respectively.

An imaging system may include an image sensor having pixels with stacked photodiodes in which a first photodiode generates a first image signal in response to light of a first wavelength and a second photodiode generates a second image signal in response to light of a second wavelength. The imaging system may include processing circuitry that applies a color correction matrix to isolate components of the first and second signals that are generated in response to light of the first and second wavelengths while removing components of the first and second signals that are generated in response to light of other wavelengths. The processing circuitry may increase noise correlations between the signals to mitigate noise amplification generated by the color correction matrix. The processing circuitry may apply a point filter to increase luma fidelity of the signals.

A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.

A display apparatus includes a data line, a first voltage line extending in parallel to the data line, a scan line extending in a direction perpendicular to the data line, a second voltage line extending in parallel to the scan line, and a line extending in parallel to the data line or the scan line. A portion of the line parallel to the scan line overlaps the second voltage line.

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Disclosed are a pixel amplification apparatus and a CMOS image sensor thereof. The pixel amplification apparatus includes a pixel bias sampling unit that samples a first pixel bias voltage, a pixel bias current supply unit that supplies an output node of a pixel signal with a first pixel bias current based on a sampled bias voltage outputted from the pixel bias sampling unit, and a pixel bias current adding unit that additionally supplies the output node with a second pixel bias current in response to a second pixel bias voltage and a period control signal.

An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered.

A skill-based progressive interleaved wagering system is disclosed, including an interactive controller connected to an application controller, and configured to: communicate application telemetry; receive application credit (AC) information and a wager outcome; communicate an indication to purchase a ticket; display ticket information; communicate an indication to use the ticket; provide the secondary application; communicate secondary telemetry; receive and display certificate information; a wager controller connected to the application controller, and constructed to: receive wager request instructions; determine and communicate the wager outcome; and the application controller connecting the interactive controller and the wager controller, connected to a session controller, and constructed to: receive application telemetry and the wager outcome; receive indication to purchase the ticket; communicate ticket purchase; receive ticket; receive indication to use the ticket; communicate ticket consumption; receive the secondary telemetry; determine whether AC should be awarded from a progressive pool of AC; receive the certificate.

A first semiconductor element according to one embodiment of the present disclosure includes: an element substrate including an element region in which a wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack, and a peripheral region outside the element region; a readout circuit substrate opposed to the first semiconductor layer with the wiring layer interposed therebetween, and electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween; a first electrode provided in the wiring layer and electrically coupled to the first semiconductor layer; a second electrode opposed to the first electrode with the first semiconductor layer interposed therebetween; and an insulating layer provided on the second electrode and having a non-reducing property.