A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

An overall displacement tolerance applicable to each pixel tile in a plurality of pixel tiles to be used as parts of an image rendering surface is determined. Each pixel tile in the plurality of pixel tiles comprises a plurality of sub-pixels. Random displacements are generated in each pixel tile in the plurality of pixel tiles based on the overall displacement tolerance. The plurality of image rendering tiles with the random displacements are combined into the image rendering surface.

The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

A nitride-based semiconductor light-emitting element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type; a carrier blocking layer of the second conductivity type, provided on a surface of the second semiconductor layer closer to the first semiconductor layer; and a light-emitting layer region having a light-emitting layer, provided between the first semiconductor layer and the carrier blocking layer. A predetermined specific region is provided in the carrier blocking layer and extending from an interface between the carrier blocking layer and the light-emitting layer region and wherein a maximum value of a concentration of an impurity of the second conductivity type in the predetermined specific region is higher than 5×10.sup.19 cm.sup.−3.

A vertical light-emitting diode device and a method of fabricating the same are provided. The device may include a conductive substrate serving as a p electrode, a p-type GaN layer provided on the conductive substrate, an active layer provided on the p-type GaN layer, an n-type GaN layer provided on the active layer, an n electrode pattern provided on the n-type GaN layer, a metal oxide structure filling a plurality of holes formed in the n-type GaN layer, and a seed layer provided on bottom surfaces of the holes and used to as a seed in a crystal growth process of the metal oxide structure.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.

A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.

A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.