An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

A circuit board is provided in which a transmission loss is reduced. The circuit board includes a first layer; a transmission line disposed on the first layer; and a second layer stacked with the first layer. The second layer includes a first region, which is constructed of a first material, corresponding to a position of the transmission line, and a second region, which is constructed of a second material having a permittivity that is different from that of the first material, corresponding to the position of the transmission line.

An antenna comprising: a variable dielectric constant (VDC) layer; a plurality of radiating patches provided over the VDC layer; a plurality of signal lines, each terminating in alignment below one of the radiating patches; a plurality of control lines, each corresponding to one of the signal lines; a ground plane; wherein the VDC layer comprises: a polymer dispersed liquid crystal (PDLC) layer or a PDLC layer in a polymerized and sheared state.

Various examples related to metaconductor based skins and transmission lines are provided. In one example, a flexible metaconductor skin includes a flexible substrate; at least one layer of non-ferromagnetic metal disposed on the flexible substrate; and a layer of ferromagnetic metal disposed on the at least one layer of non-ferromagnetic metal. The flexible metaconductor skin can be used as a multi-layer coplanar waveguide (CPW) transmission line.

A coplanar waveguide transmission line and a design method thereof are provided. The coplanar waveguide transmission line includes a first dielectric substrate, a center conductor strip, and two ground conductor strips. The first dielectric substrate has a first surface and a second surface opposite to each other. The center conductor strip and the ground conductor strips are stacked and fixed to the first surface. The center conductor strip includes a first segment and a second segment. A width of the first segment is greater than a width of the second segment, so that the first segment and the second segment form a step structure. A rectangular groove recessed toward the second surface is defined in the first surface, and a part of the center conductor strip is stacked and fixed to a side, distal from the second surface, of the rectangular groove to form a defected ground structure.

A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed.

A qubit device includes an elongated thin film uninterrupted by Josephson junctions, a quantum device in electrical contact with a proximal end of the elongated thin film, and a ground plane that is co-planar with the elongated thin film and is in electrical contact with a distal end of the elongated thin film, in which the thin film, the quantum device, and the ground plane comprise a material that is superconducting at a designed operating temperature.

A quantum device includes: a substrate; and at least three co-planar structures arranged on a surface of the substrate, each co-planar structure, of the at least three co-planar structures, including a superconductor, in which a first effective dielectric constant between a first co-planar structure and a second co-planar structure that is a nearest neighbor to the first co-planar structure is above a first threshold, a second effective dielectric constant between the first co-planar structure and a third co-planar structure that is a next nearest neighbor to the first so-planar structure is less than a second threshold, and the second threshold is less than the first threshold.

A chip comprising a bonding pad region and a transmission section. The bonding pad region has a first impedance, and is configured for electrical connection to an external transmission line. The transmission section extends away from the bonding pad region and has a second impedance. The bonding pad region is configured to enable field confinement and field matching between the bonding pad region and the external transmission line, and the second impedance is not equal to the first impedance.

A communication module may include a communication ground layer. The communication module may also include a circuit board. The circuit board may be located proximate the communication ground layer. The circuit board may include a stitch layer. The stitch layer may be electrically coupled to the communication ground layer via a plurality of stitch layer vias. Additionally, the communication module may include multiple ground vias. The ground vias may be electrically coupled to a portion of the circuit board and to the communication ground layer.