Aspects of methods and systems for high frequency signal selection are provided. The system for high frequency signal selection comprises a first driver and a second driver. The first driver is able to receive a first high frequency input, and the second driver is able to receive a second high frequency input. The output of the first driver is operably coupled, via a first inductive element, to a first resistive load and a first buffer, and the second driver is operably coupled, via a second inductive element, to the output of the first driver. One or both of the first high frequency input and the second high frequency input may be transferred to the first buffer by selectively enabling a current to one or both of the first driver and the second driver, respectively.

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again.

A transceiver device 100 includes a transmit path module 110, a receive path module 120 and a compensation signal generator module 130. The transmit path module 110 generates a high frequency transmit signal 112 based on a baseband transmit signal. The receive path module 120 generates a baseband receive signal 122 based on a received high frequency receive signal 114. Further, the compensation signal generator module 130 generates a compensation signal 132 comprising at least one signal portion with a frequency equal to a frequency of an undesired signal portion of the baseband receive signal 122 caused by an undesired signal portion within the high frequency transmit signal 112 comprising a frequency equal to an integer multiple larger than 1 of a transmit frequency of the high frequency transmit signal 112.

A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value.

The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.

Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

A gate drive circuit creates a bipolar voltage to a gate of an IGB power transistor, and compensates for Miller currents of the IGB power transistor. The compensating is performed by a switching element connected in series with a capacitor between the gate (X4) and a supply voltage.

A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

The calculator calculates the remainder of the division of which the dividend is the minimum accumulated value at which a carryover occurs in the modulator and the devisor is a fractional set value, and calculates the quotient and remainder of the division of which the dividend is the devisor of the previous division and the devisor is the remainder of the previous division until the remainder becomes zero. The abnormal noise determiner determines that the fractional set value causes periodic abnormal noise based on the quotients calculated by the calculator using the fractional set value. The fractional setter sets in the modulator the fractional set value changed to the extent that the output frequency of the VCO does not exceed a given value when the abnormal noise determiner determines that the changed fractional set value does not cause periodic abnormal noise.