Systems and methods for a track and hold amplifier with extended dynamic range may include a track amplifier comprising a first PMOS transistor coupled to a first NMOS transistor, a second PMOS transistor coupled to a second NMOS transistor, a capacitor at gates of each NMOS and PMOS transistor, and a plurality of switches. The track and hold amplifier is operable to, during a tracking mode of the track and hold amplifier, couple a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate of the first PMOS transistor and a second capacitor coupled to the gate of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate of the second PMOS and a fourth capacitor coupled to the gate of the second NMOS transistor.

The amplifier includes an input circuit configured to convert an input signal into a current; an output circuit comprising at least one switching element for reducing a voltage change of an output end of the input circuit and configured to provide an output signal; and a biasing circuit connected to the at least one switching element to form a feedback loop for reducing the voltage change of the output end of the input circuit.

An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

In at least one example, a circuit includes an amplifier, a first feedback loop, and a second feedback loop. The amplifier includes an amplifier input and an amplifier output. The first feedback loop includes a first feedback capacitor and a first switch. The first feedback loop is coupled between the amplifier input and the amplifier output. The first feedback capacitor is coupled to the amplifier output through the first switch. The second feedback loop includes a second feedback capacitor and a second switch. The second feedback loop is coupled in parallel with the first feedback loop between the amplifier input and the amplifier output. The second feedback capacitor is coupled to the amplifier input and to the first feedback capacitor through the second switch.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)(W).

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

An amplifying apparatus includes a variable gain amplifying circuit configured to operate in a gain mode selected from a plurality of gain modes in response to a first control signal during operation in an amplification mode, a variable attenuation circuit configured to have an attenuation value that is adjusted in response to a second control signal, and a phase compensation value which compensates for a phase distortion in the selected gain mode, and a control circuit configured to control the selecting of the gain mode, the adjusting of the attenuation value and the phase compensation value, based on the first and second control signals.

Power amplifier module with power supply control. A power amplification control system can include an interface configured to receive a transceiver control signal from a transceiver. The power amplification control system can include a power amplifier control component configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver and a power supply control component configured to generate a power supply control signal based on the transceiver control signal from the transceiver and to generate the power supply control signal based on a local control signal from the power amplifier control component.