A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

A variable gain transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner. A variable gain circuit may include the variable gain transconductance amplifier.

Attenuators having phase shift and gain compensation circuits. In some embodiments, a radio-frequency (RF) attenuator circuit can include one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path. The RF attenuator circuit can further include a global bypass path implemented between the input node and the output node. The RF attenuator circuit can further include a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

Disclosed examples include programmable gain amplifier (PGA) circuits with an operation amplifier circuit having a first amplifier input and a second amplifier input including a plurality of second input nodes, a resistor array including a plurality of resistor sections connected in series with one another between the amplifier output and a reference voltage node, and a trim select circuit coupled between the second amplifier input and the resistor array circuit to deliver a feedback voltage signal to each individual one of the second input nodes from a given selected one of a plurality of the tap points of the resistor array circuit according to a trim code to provide analog gain trimming by interpolation.

A compensation circuit includes an amplifier coupled between a first voltage terminal and a common terminal. The amplifier has a first output terminal. A current source transistor has a current path coupled between a second voltage terminal and a second output terminal. A threshold voltage sense transistor has a current path coupled between the first and second output terminals. A gate and drain of the threshold voltage sense transistor are connected. An output transistor having a current path coupled between the first output terminal and a third output terminal has a gate coupled to the second output terminal.

A wireless receiver automatic gain control system includes: a coarse amplification subsystem that receives and amplifies a carrier-modulated signal; a demodulator that generates a baseband signal from the amplified carrier-modulated signal; a fine amplification subsystem that amplifies the baseband signal; and a controller connected to the amplification subsystems. The controller: obtains a unified gain value for the amplification subsystems; based on the unified gain value, selects (i) one of a plurality of coarse gain values defining a set of coarse gain steps each spanning a plurality of unified gain steps, and (ii) one of a plurality of fine gain values defining a set of fine gain steps each spanning a single unified gain step; and sets (i) the gain of the coarse amplification subsystem to the selected coarse gain value, and (ii) the gain of the fine amplification subsystem to the selected fine gain value.

A wireless receiver automatic gain control system includes: a coarse amplification subsystem that receives and amplifies a carrier-modulated signal; a demodulator that generates a baseband signal from the amplified carrier-modulated signal; a fine amplification subsystem that amplifies the baseband signal; and a controller connected to the amplification subsystems. The controller: obtains a unified gain value for the amplification subsystems; based on the unified gain value, selects (i) one of a plurality of coarse gain values defining a set of coarse gain steps each spanning a plurality of unified gain steps, and (ii) one of a plurality of fine gain values defining a set of fine gain steps each spanning a single unified gain step; and sets (i) the gain of the coarse amplification subsystem to the selected coarse gain value, and (ii) the gain of the fine amplification subsystem to the selected fine gain value.

Disclosed is a frequency doubler which controls a magnitude of a signal supplied to a virtual ground by adjusting a gain of one-side transistor among transistors receiving differential input signals when outputting a frequency multiplied LO signal through the virtual ground by amplifying the input differential signals by using a differential circuit structure to minimize undesired harmonics characteristics in a frequency doubled signal output by making the magnitudes of two differential signals be the same as each other.

A power amplifier gain switching circuit includes: a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal; an amplifier including: a bias input terminal configured to receive an external bias voltage; a signal input terminal configured to receive the first input signal; a control terminal configured to receive the control signal; and an output terminal configured to output an output signal with a gain; wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.