A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.

Various signal processing techniques may benefit from appropriate handling. For example, certain signal processors may benefit from quarter wavelength unit delay and complex weight coefficient continuous-time filters. A method can include splitting an input signal into a plurality of signal paths. The method can also include complex weighting, for each signal path, a respective signal. The method can further include summing outputs of the signal paths. The method can additionally include providing an output comprising the sum of the signal paths. The complex weighting can be configured to independently control gain, phase and delay of the output signal over broadband.

Various signal processing techniques may benefit from appropriate handling. For example, certain signal processors may benefit from quarter wavelength unit delay and complex weight coefficient continuous-time filters. A method can include splitting an input signal into a plurality of signal paths. The method can also include complex weighting, for each signal path, a respective signal. The method can further include summing outputs of the signal paths. The method can additionally include providing an output comprising the sum of the signal paths. The complex weighting can be configured to independently control gain, phase and delay of the output signal over broadband.

A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.