A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x).sup.2 per stage. It also uses a g.sub.m cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7.sup.th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x).sup.2 per stage. It also uses a g.sub.m cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7.sup.th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

A filter circuit includes a filter having an input and an output at which an output of the filter is provided, a step detector coupled to receive an input signal at the input of the filter and configured to detect a predetermined step in the input signal and to assert a bypass signal in response to detection of the predetermined step. A logic circuit is responsive to the bypass signal and configured to cause the input signal to be coupled to the output of the filter without filtering when the bypass signal is asserted.

A magnet-free non-reciprocal device realized using modulated filters. The device includes one or more filters in one or more branches, where each branch connects two ports or a port and a central node. The poles and zeros of each of the first, second and third filters are modulated in time such that degenerate modes at each pole and zero is split thereby destructively interfering at one or more output ports and adding up at another output port allowing non-reciprocal transmission, isolation and/or non-reciprocal phase shift. The device is able to realize a magnet-free full-duplex communication scheme implementing a magnet-free circulator for radio frequency cancellation or a magnet-free isolator or gyrator.

A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system.

Magnetic field sensors and associated techniques use a Hall effect element in a current spinning arrangement in combination with a rippled reduction feedback network configured to reduce undesirable spectral components generated by the current spinning and other circuit elements.

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

A system and method for controlling current-range switching to limit glitching includes a sense array connected between an input and a load. The sense array includes a parallel first and second branch circuits. The first branch circuit includes at least one first transistor, a first sense resistor, and a variable impedance control circuit. The variable impedance control circuit is configured to receive a control signal and generate a gate voltage of the at least one first transistor to establish an impedance of the sense array between the input and the load that is proportional to the control signal, including controlling the gate voltage of the at least one first transistor such that an impedance of the sense array transitions from a first value to a second value when connecting or disconnecting the first branch circuit between the input and the load while the input is connected to the load through the second branch circuit.

A system for processing of signals with poles that are low in frequency includes a switched capacitor circuit that includes two switches connected to an input and an output of a switching capacitor (C.sub.s), respectively, in an alternating manner at a selected switching frequency (f.sub.SW); and a filter capacitor connected between an input and the switched capacitor circuit. The filter capacitor and the switched capacitor circuit together function as a filter, thereby a pole frequency depending on a ratio of capacitance of the switching capacitor (C.sub.s) and the filter capacitor, instead of an RC product.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.